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Contents

README

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INA186A1IDCKR

Texas Instruments · Current-Sensing Amplifiers · SC-70-6

INA186A1IDCKR from Texas Instruments, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Reference input. Sets the output voltage offset to enable bidirectional current sensing; drive with an external voltage (typically VS/2 for bidirectional, GND for unidirectional). Available only in DCK (SC70) and DDF (SOT-23) packages.
2 GND power_in Device ground / analog return.
3 VS power_in Power supply input, 1.7 V to 5.5 V. Bypass to GND with a 0.1 µF capacitor.
4 IN+ input Non-inverting current-sense input. Connect to the bus-side of the shunt resistor for high-side sensing, or to the load-side for low-side sensing. Common-mode range -0.2 V to +40 V, independent of VS.
5 IN- input Inverting current-sense input. Connect to the load-side of the shunt resistor for high-side sensing, or to ground-side for low-side sensing.
6 OUT output Analog voltage output. VOUT = (VIN+ - VIN-) × Gain + VREF. Gain is 25 V/V for the INA186A1 variant.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SC-70-6
Category Op-amp/Cmp
Pins 6

Ordering variants

Same part, different packaging or reel option.

  • INA186A1IDCKR
  • INA186A1IDCKT
  • INA186A1IDCKRIDDFR
  • INA186A1IDCKRIDDFT
  • INA186A1IDCKRIYFDR
  • INA186A1IDCKRIYFDT

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Common-mode rejection ratio CMRR 120 150 dB VSENSE = 0mV,VIN+ = –0.1V 至 40V,TA = –40°C 至 +125°C 5
Offset voltage, RTI VOS -50 -3 50 µV VS = 1.8V,VSENSE = 0mV 5
Offset drift, RTI dVOS/dT 0.05 0.5 µV/°C VSENSE = 0V,TA = –40°C 至 +125°C 5
Power-supply rejection ratio, RTI PSRR -10 -1 10 µV/V VSENSE = 0mV,VS = 1.7V 至 5.5V 5
Input bias current IIB 0.5 3 nA VSENSE = 0mV 5
Input offset current IIO -0.07 0.07 nA VSENSE = 0mV 5
Gain error EG -1 -0.04 1 % VOUT = 0.1 V 至 VS – 0.1 V 5
Gain error drift 2 10 ppm/°C TA=-40°C 至 +125°C 5
Nonlinearity error -0.01 0.01 % VOUT = 0.1 V 至 VS – 0.1 V 5
Reference voltage rejection ratio RVRR -10 2 10 µV/V VREF = 100mV 至 VS – 100mV,TA = –40°C 至 +125°C 5
Maximum capacitive load 1 nF 无持续振荡 5
Output swing to GND VSN 0.05 1 mV VS = 1.8V,RL = 10kΩ 至 GND,TA = –40°C 至 +125°C,VSENSE = –10mV,VREF = 0V 5
Zero-current output voltage VZL 2 10 mV VS = 1.8V,RL = 10kΩ 至 GND,TA = –40°C 至 +125°C,VSENSE = 0mV,VREF = 0V 5
Quiescent current IQ 48 65 µA VS = 1.8V,VSENSE = 0mV 6
Quiescent current over temperature IQ 90 µA VS = 1.8V,VSENSE = 0mV,TA = –40°C 至 +125°C 6
Common-mode input voltage range VCM 40 V 4
Input pin voltage range (VIN+, VIN–) VIN+, VIN– 40 V 4
Operating supply voltage VS 1.7 5.5 V 4
Operating temperature (natural ventilation) TA -40 125 °C 自然通风 4
Supply voltage VS 6 V 4
Differential input voltage (VIN+) – (VIN–) (VIN+) – (VIN–) -42 42 V 4
Analog input voltage relative to GND VIN+, VIN– 42 V 4
Input current into any pin 5 mA 4
Operating temperature (absolute maximum) TA -55 150 °C 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
ESD, human body model (HBM) V(ESD) -3000 3000 V ANSI/ESDA/JEDEC JS-001 4
ESD, charged device model (CDM) V(ESD) -1000 1000 V JEDEC JESD22-C101 4
Gain (A1 device) G 25 V/V 5
Bandwidth (A1 device) BW 45 kHz A1 器件,CLOAD = 10pF 5
Slew rate SR 0.3 V/µs VS = 5.0V,VOUT = 0.5V 至 4.5V 5
Settling time tS 30 µs 从电流阶跃到最终值的 1% 以内 5
Voltage noise density, RTI 75 nV/√Hz 5
Thermal resistance, junction-to-ambient (DCK) RθJA 170.7 °C/W DCK (SC70) 6-pin 4
Thermal resistance, junction-to-case (top) (DCK) RθJC(top) 132.7 °C/W DCK (SC70) 6-pin 4
Thermal resistance, junction-to-board (DCK) RθJB 65.3 °C/W DCK (SC70) 6-pin 4
Junction-to-top characterization parameter (DCK) ΨJT 45.7 °C/W DCK (SC70) 6-pin 4
Junction-to-board characterization parameter (DCK) ΨJB 65.2 °C/W DCK (SC70) 6-pin 4

CAD (KiCad official)

  • Symbol: INA186A1IDCKR
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SC-70-6 (KiCad packages3D, STEP)
  • 3D model files: ina186a1idckr-etched.step / ina186a1idckr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ina186a1idckr.step / ina186a1idckr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 1517831c6395c89f, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF