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INA125U

Texas Instruments · Instrumentation Amplifiers · SOIC-16

INA125U from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V+ power_in Positive power supply voltage: 2.7V to 36V single supply or ±1.35V to ±18V dual supply.
2 SLEEP input Logic input for shutdown mode; logic low (≤100mV) enables sleep mode with quiescent current dropping to approximately 1µA; wake-up time 150µs.
3 V- power_in Negative power supply voltage; connected to ground in single supply operation or to negative supply in dual supply operation.
4 VREFOUT output Precision voltage reference output; connect to VREFBG (1.24V), VREF2.5, VREF5, or VREF10 pins to select output reference voltage; recommended to connect even when reference not used to avoid saturating amplifier.
5 IAREF input Instrumentation amplifier reference terminal; must be connected to low impedance ground or reference voltage for proper common-mode rejection; voltage applied is added to output signal.
6 VIN+ input Non-inverting differential input; protected for ±40V input voltage; input bias current 10-25nA typical; must remain within specified input common-mode voltage range.
7 VIN- input Inverting differential input; protected for ±40V input voltage; input bias current 10-25nA typical; must remain within specified input common-mode voltage range.
8 RG passive External gain-setting resistor connection; connect resistor between pin 8 and pin 9 to set gain from 4 to 10,000 per equation G = 4 + 60kΩ/RG.
9 VREF10 passive Internal 10V reference node; connect VREFOUT to this pin to select 10V precision reference voltage with ±0.5% initial accuracy and ±35ppm/°C drift.
10 VREF5 passive Internal 5V reference node; connect VREFOUT to this pin to select 5V precision reference voltage with ±0.5% initial accuracy and ±35ppm/°C drift.
11 VREF2.5 passive Internal 2.5V reference node; connect VREFOUT to this pin to select 2.5V precision reference voltage with ±0.5% initial accuracy and ±35ppm/°C drift.
12 VREFBG passive Bandgap reference voltage node (1.24V ±0.5%); connect VREFOUT to this pin to output the precision bandgap reference voltage.
13 VREFCOM power_in Reference common terminal; approximately 180µA flows out of this terminal; connect through low impedance path to sensor common to avoid ground loop problems.
14 VO output Single-ended amplifier output; output voltage swing (V+)-0.9V to (V-)+0.4V for ±15V supplies; short-circuit current ±9 to ±12mA; load capacitance up to 1000pF.
15 Sense input Bridge output sense connection for bridge measurement and transducer applications; enables feedback path for gain setting and error correction.
16 RG passive External gain-setting resistor connection; second terminal of gain-setting resistor connected between pin 8 and pin 16 (or pin 9 per functional description).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Amplifiers/Comparators
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Voltage, RTI Initial -250 50 250 µV 2
Offset Voltage vs Temperature -2 0.25 2 µV/°C 2
Offset Voltage vs Power Supply -20 3 20 µV/V VS = ±1.35V to ±18V, G = 4 2
Common-Mode Rejection, G = 4 78 84 dB VCM = -10.7V to +10.2V, G = 4 2
Common-Mode Rejection, G = 10 86 94 dB VCM = -10.7V to +10.2V, G = 10 2
Common-Mode Rejection, G = 100 100 114 dB VCM = -10.7V to +10.2V, G = 100 2
Common-Mode Rejection, G = 500 100 114 dB VCM = -10.7V to +10.2V, G = 500 2
Bias Current 10 25 nA VCM = 0V 2
Offset Current -2.5 0.5 2.5 nA 2
Range of Gain 4 10000 V/V 2
Gain Error, G = 4 -0.075 0.01 0.075 % VO = -14V to +13.3V, G = 4 2
Gain Error, G = 10 -0.3 0.03 0.3 % VO = -14V to +13.3V, G = 10 2
Gain Error, G = 100 -0.5 0.05 0.5 % VO = -14V to +13.3V, G = 100 2
Gain vs Temperature, G = 4 -15 1 15 ppm/°C G = 4 2
Gain vs Temperature, G > 4 -100 25 100 ppm/°C G > 4 (note 1) 2
Nonlinearity, G = 4 -0.002 0.0004 0.002 % of FS VO = -14V to +13.3V, G = 4 2
Nonlinearity, G = 10 -0.002 0.0004 0.002 % of FS VO = -14V to +13.3V, G = 10 2
Nonlinearity, G = 100 -0.01 0.001 0.01 % of FS VO = -14V to +13.3V, G = 100 2
Short-Circuit Current -9 12 mA 2
Voltage Reference Accuracy -0.5 0.15 0.5 % IL = 0 2
Voltage Reference vs Temperature -35 18 35 ppm/°C IL = 0 2
Voltage Reference vs Power Supply -50 20 50 ppm/V V+ = (VREF + 1.25V) to +36V 2
Voltage Reference vs Load 3 75 ppm/mA IL = 0 to 5mA 2
Dropout Voltage, (V+), VREF 1.25 1 V Ref Load = 2kΩ 2
Specified Voltage Range 1.35 18 V 3
Quiescent Current, Positive 460 525 µA IO = IREF = 0mA 3
Quiescent Current, Negative -280 -325 µA IO = IREF = 0mA 3
Sleep Current -25 1 25 µA VSLEEP ≤ 100mV; RL = 10kΩ, Ref Load = 2kΩ 3
Logic High Input Voltage (sleep pin) VIH 2.7 V 3
Logic Low Input Voltage (sleep pin) VIL 0 0.1 V 3
Specification Range -40 85 °C 3
Operation Range -55 125 °C 3
Storage Range -55 125 °C 3
Offset Voltage, RTI Initial (VS = +5V) -500 75 500 µV VS = +5V 3
Offset Voltage vs Power Supply (VS = +5V) 3 20 µV/V VS = +2.7V to +36V 3
Common-Mode Rejection, G = 4 (VS = +5V) 78 84 dB VCM = +1.1V to +3.6V, G = 4 3
Common-Mode Rejection, G = 10 (VS = +5V) 86 94 dB VCM = +1.1V to +3.6V, G = 10 3
Common-Mode Rejection, G = 100 (VS = +5V) 100 114 dB VCM = +1.1V to +3.6V, G = 100 3
Common-Mode Rejection, G = 500 (VS = +5V) 100 114 dB VCM = +1.1V to +3.6V, G = 500 3
Operating Voltage Range 2.7 36 V 3
Quiescent Current (VS = +5V) 460 525 µA IO = IREF = 0mA 3
Sleep Current (VS = +5V) -25 1 25 µA VSLEEP ≤ 100mV; RL = 10kΩ, Ref Load = 2kΩ 3
Power Supply Voltage, V+ to V- 36 V 4
Input Signal Voltage -40 40 V 4
Operating Temperature -55 125 °C 4
Storage Temperature -55 125 °C 4
Lead Temperature 300 °C soldering, 10s 4
Thermal Resistance, θJA (SO-16 Surface-Mount) θJA 100 °C/W 3

CAD (KiCad official)

  • Symbol: INA125U
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ina125u-etched.step / ina125u-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ina125u.step / ina125u.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 1b5f35fb0b06a5ef, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF