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IL 712S-3E

Public Made by Adom

by adom

NVE Digital Isolators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsignal isolation devicesil 712s-3efactory-2.0.0extractor-text
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Contents

README

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IL 712S-3E

NVE · Digital Isolators · SOIC-8

IL 712S-3E from NVE, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD1 power_in Supply voltage for side 1, 2.7 V to 5.5 V, decoupled with 0.1 µF typical (0.047 µF minimum) capacitor close to the pin.
2 IN1 input Data input, channel 1 (logic high 2.4 V to VDD, logic low 0 to 0.8 V).
3 OUT2 output Data output, channel 2 (VOH min 0.8 x VDD at -4 mA, VOL max 0.8 V at 4 mA).
4 GND1 power_in Ground return for VDD1.
5 GND2 power_in Ground return for VDD2.
6 IN2 input Data input, channel 2 (logic high 2.4 V to VDD, logic low 0 to 0.8 V).
7 OUT1 output Data output, channel 1 (VOH min 0.8 x VDD at -4 mA, VOL max 0.8 V at 4 mA).
8 VDD2 power_in Supply voltage for side 2, 2.7 V to 5.5 V, decoupled with 0.1 µF typical (0.047 µF minimum) capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer NVE
Package SOIC-8
Category Signal Isolation Devices
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD1, VDD2 2.7 5.5 V 2
Ambient Operating Temperature TA -40 100 °C IL712S 2
Junction Temperature (operating) TJ -40 110 °C IL712S 2
Logic High Input Voltage VIH 2.4 V max VDD 2
Logic Low Input Voltage VIL 0 0.8 V 2
Input Signal Rise and Fall Times tIR, tIF 1 μs 2
Storage Temperature TS -55 150 °C 2
Junction Temperature TJ -55 150 °C 2
Ambient Operating Temperature TA -55 130 °C 2
Supply Voltage VDD1, VDD2 -0.5 7 V 2
Input Voltage VI -0.5 V max VDD + 0.5 2
Output Voltage VO -0.5 V max VDD + 0.5 2
Output Current Drive IO 10 mA 2
Lead Solder Temperature 260 °C 10 sec. 2
ESD 2 kV HBM 2
Input Quiescent Supply Current (3.3 V) IDD1 1.2 1.75 mA IL712/IL721, 3.3 V 6
Output Quiescent Supply Current (3.3 V) IDD2 1.2 1.75 mA IL712/IL721, 3.3 V 6
Logic Input Current (3.3 V) II -10 10 μA 3.3 V 6
Logic Low Output Voltage (3.3 V) VOL 0 0.1 V IO = 20 μA, VI = VIL 6
Logic Low Output Voltage (3.3 V) VOL 0.5 0.8 V IO = 4 mA, VI = VIL 6
Maximum Data Rate (3.3 V) 130 140 Mbps IL711S/IL712S, CL = 15 pF 6
Propagation Delay High to Low (3.3 V) tPHL 12 18 ns CL = 15 pF 6
Propagation Delay Low to High (3.3 V) tPLH 12 18 ns CL = 15 pF 6
Pulse Width Distortion (3.3 V) PWD 2 3 ns IL711S/IL712S, CL = 15 pF 6
Propagation Delay Skew (3.3 V) tPSK 4 6 ns CL = 15 pF 6
Output Rise Time (3.3 V) tR 2 4 ns 10%-90%, CL = 15 pF 6
Output Fall Time (3.3 V) tF 2 4 ns 10%-90%, CL = 15 pF 6
Common Mode Transient Immunity (3.3 V) /CMH/,/CML/ 100 150 kV/µs Per IEC 60747 6
Channel-to-Channel Skew (3.3 V) tCSK 2 3 ns CL = 15 pF 6
Dynamic Power Consumption, input side (3.3 V) 140 240 μA/Mbps/ch 6
Dynamic Power Consumption, output side (3.3 V) 20 40 μA/Mbps/ch 6
Input Quiescent Supply Current (5 V) IDD1 1.8 2.5 mA IL712/IL721, 5 V 7
Output Quiescent Supply Current (5 V) IDD2 1.8 2.5 mA IL712/IL721, 5 V 7
Logic Input Current (5 V) II -10 10 μA 5 V 7
Logic Low Output Voltage (5 V) VOL 0 0.1 V IO = 20 μA, VI = VIL 7
Logic Low Output Voltage (5 V) VOL 0.5 0.8 V IO = 4 mA, VI = VIL 7
Maximum Data Rate (5 V) 130 150 Mbps IL711S/IL712S, CL = 15 pF 7
Propagation Delay High to Low (5 V) tPHL 10 15 ns CL = 15 pF 7
Propagation Delay Low to High (5 V) tPLH 10 15 ns CL = 15 pF 7
Pulse Width Distortion (5 V) PWD 2 3 ns IL711S/IL712S, CL = 15 pF 7
Pulse Jitter tJ 100 ps CL = 15 pF 7
Propagation Delay Skew (5 V) tPSK 4 6 ns CL = 15 pF 7
Output Rise Time (5 V) tR 1 3 ns 10%-90%, CL = 15 pF 7
Output Fall Time (5 V) tF 1 3 ns 10%-90%, CL = 15 pF 7
Common Mode Transient Immunity (5 V) /CMH/,/CML/ 100 150 kV/µs Per IEC 60747 7
Channel to Channel Skew (5 V) tCSK 2 3 ns CL = 15 pF 7
Dynamic Power Consumption (5 V) 200 340 μA/Mbps per channel 7
Junction-Ambient Thermal Resistance, 0.15" SOIC8 θJA 134 °C/W Double-sided PCB in free air 8
Junction-Case (Top) Thermal Resistance, 0.15" SOIC8 θJC 10 °C/W Double-sided PCB in free air 8
Power Dissipation, 0.15" SOIC8 PD 675 mW 8
Creepage Distance, SOIC8 4.03 mm external 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin Blank = 80/20 Tin/Lead Plating E = RoHS Compliant 16

CAD (KiCad official)

  • Symbol: IL 712S-3E
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: il-712s-3e-etched.step / il-712s-3e-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); il-712s-3e.step / il-712s-3e.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NVE datasheet (20 pp, sha256 e88a45f7f9c72ad1, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF