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IKCM15L60GD
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Infineon Technologies Motor Driver ICs, DIP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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IKCM15L60GD
Infineon Technologies · Motor Driver ICs · DIP-24
IKCM15L60GD from Infineon Technologies, in a DIP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS(U) | power_in | U-phase high-side floating IC supply offset; VS(U) is robust to a transient negative voltage of -50V with respect to VSS and the high-side circuit floats with the external high-side emitter voltage. |
| 2 | VB(U) | power_in | U-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 3 | VS(V) | power_in | V-phase high-side floating IC supply offset; VS(V) is robust to a transient negative voltage of -50V with respect to VSS. |
| 4 | VB(V) | power_in | V-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 5 | VS(W) | power_in | W-phase high-side floating IC supply offset; VS(W) is robust to a transient negative voltage of -50V with respect to VSS. |
| 6 | VB(W) | power_in | W-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 7 | HIN(U) | input | U-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 8 | HIN(V) | input | V-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 9 | HIN(W) | input | W-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 10 | LIN(U) | input | U-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 11 | LIN(V) | input | V-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 12 | LIN(W) | input | W-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 13 | VDD | power_in | Low-side control supply for input logic and output power stage; operation at power-on needs at least 12.1V typ, and all gate drivers shut down when VDD falls below 10.4V typ. |
| 14 | VFO | output | Fault output and direct NTC access referenced to VSS; it is an open-drain output that indicates VDD under-voltage or a triggered over-current at ITRIP and requires an external pull-up resistor. |
| 15 | ITRIP | input | Over-current shutdown input referenced to VSS with a comparator threshold of 400 to 540mV (470mV typ) and a typical 530ns input noise filter, shutting down all outputs after a typical 1000ns propagation delay. |
| 16 | VSS | power_in | Low-side control negative supply and reference ground for the input logic and the VFO/ITRIP thresholds. |
| 17 | NW | passive | W-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 18 | NV | passive | V-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 19 | NU | passive | U-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 20 | W | output | Motor W-phase connection, forming the high-side emitter and low-side collector of the W leg. |
| 21 | V | power_in | Motor V-phase connection, forming the high-side emitter and low-side collector of the V leg. |
| 22 | U | output | Motor U-phase connection, forming the high-side emitter and low-side collector of the U leg. |
| 23 | P | power_in | Positive DC bus input to the high-side IGBTs; the bus voltage must not exceed 450V (surge limit 500V). |
| 24 | NC | unconnected | No connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | DIP-24 |
| Category | Power Management ICs |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | Tstg | -40 | 125 | °C | 7 | ||
| Isolation test voltage | VISOL | 2000 | V | RMS, f = 60Hz, t = 1min | 7 | ||
| Operating case temperature range | TC | -40 | 125 | °C | Refer to Figure 6 | 7 | |
| Max. blocking voltage | VCES | 600 | V | IC = 250µA | 7 | ||
| DC link supply voltage of P-N | VPN | 450 | V | Applied between P-N | 7 | ||
| DC link supply voltage (surge) of P-N | VPN(surge) | 500 | V | Applied between P-N | 7 | ||
| Output current | IC | -15 | 15 | A | TC = 25°C, TJ < 150°C | 7 | |
| Maximum peak output current | IC(peak) | -30 | 30 | A | TC = 25°C, less than 1ms | 7 | |
| Short circuit withstand time | tSC | 5 | µs | VDC ≤ 400V, TJ = 150°C | 7 | ||
| Power dissipation per IGBT | Ptot | 58.6 | W | 7 | |||
| Operating junction temperature range | TJ | -40 | 150 | °C | 7 | ||
| Single IGBT thermal resistance, junction-case | RthJC | 2.13 | K/W | 7 | |||
| Single diode thermal resistance, junction-case | RthJCD | 3.42 | K/W | 7 | |||
| Module supply voltage | VDD | -1 | 20 | V | 7 | ||
| High side floating supply voltage (VB vs. VS) | VBS | -1 | 20 | V | 7 | ||
| Input voltage LIN, HIN, ITRIP | VIN | -1 | 10 | V | 7 | ||
| Switching frequency | fPWM | 20 | kHz | 7 | |||
| DC link supply voltage of P-N | VPN | 0 | 400 | V | 8 | ||
| High side floating supply voltage (VB vs. VS) | VBS | 13.5 | 18.5 | V | 8 | ||
| Low side supply voltage | VDD | 14.5 | 16 | 18.5 | V | 8 | |
| Control supply variation | ΔVBS | -1 | 1 | V/µs | 8 | ||
| Logic input voltages LIN, HIN, ITRIP | VIN | 0 | 5 | V | 8 | ||
| Between VSS - N (including surge) | VSS | -5 | 5 | V | 8 | ||
| Collector-Emitter saturation voltage | VCE(sat) | 1.55 | 2.1 | V | IC = 10A, TJ = 25°C | 9 | |
| Diode forward voltage | VF | 1.75 | 2.45 | V | IF = 10A, TJ = 25°C | 9 | |
| Collector-Emitter leakage current | ICES | 1 | mA | VCE = 600V | 9 | ||
| Logic "1" input voltage (LIN, HIN) | VIH | 2.1 | 2.5 | V | 9 | ||
| Logic "0" input voltage (LIN, HIN) | VIL | 0.7 | 0.9 | V | 9 | ||
| ITRIP positive going threshold | VIT,TH+ | 400 | 470 | 540 | mV | 9 | |
| ITRIP input hysteresis | VIT,HYS | 40 | 70 | mV | 9 | ||
| VDD supply under voltage positive going threshold | VDDUV+ | 10.8 | 12.1 | 13 | V | 9 | |
| VBS supply under voltage positive going threshold | VBSUV+ | 10.8 | 12.1 | 13 | V | 9 | |
| VDD supply under voltage negative going threshold | VDDUV- | 9.5 | 10.4 | 11.2 | V | 9 | |
| VBS supply under voltage negative going threshold | VBSUV- | 9.5 | 10.4 | 11.2 | V | 9 | |
| VDD supply under voltage lockout hysteresis | VDDUVH | 1 | 1.7 | V | 9 | ||
| VBS supply under voltage lockout hysteresis | VBSUVH | 1 | 1.7 | V | 9 | ||
| Quiescent VBx supply current (VBx only) | IQBS | 300 | 500 | µA | HIN = 0V | 9 | |
| Quiescent VDD supply current (VDD only) | IQDD | 370 | 900 | µA | LIN = 0V, HINX = 5V | 9 | |
| Input bias current | IIN+ | 1 | 1.5 | mA | VIN = 5V | 9 | |
| ITRIP input bias current | IITRIP+ | 65 | 150 | µA | VITRIP = 5V | 9 | |
| Fault clear time after ITRIP-fault | tFLTCLR | 40 | µs | VITRIP = 1V | 10 | ||
| Deadtime between low side and high side | DTPWM | 1.5 | µs | 10 | |||
| Repetitive peak reverse voltage | VRRM | 600 | V | 10 |
CAD (KiCad official)
- Symbol:
IKCM15L60GD - Footprint:
Package_DIP:DIP-24_W7.62mm - 3D model: DIP-24 (KiCad packages3D, STEP)
- 3D model files:
ikcm15l60gd-etched.step/ikcm15l60gd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ikcm15l60gd.step/ikcm15l60gd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Technologies datasheet (17 pp, sha256
40ab5e3310585958, retrieved 2026-10-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# IKCM15L60GD
**Infineon Technologies** · Motor Driver ICs · DIP-24
IKCM15L60GD from Infineon Technologies, in a DIP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS(U) | power_in | U-phase high-side floating IC supply offset; VS(U) is robust to a transient negative voltage of -50V with respect to VSS and the high-side circuit floats with the external high-side emitter voltage. |
| 2 | VB(U) | power_in | U-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 3 | VS(V) | power_in | V-phase high-side floating IC supply offset; VS(V) is robust to a transient negative voltage of -50V with respect to VSS. |
| 4 | VB(V) | power_in | V-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 5 | VS(W) | power_in | W-phase high-side floating IC supply offset; VS(W) is robust to a transient negative voltage of -50V with respect to VSS. |
| 6 | VB(W) | power_in | W-phase high-side floating IC supply voltage; the high-side supply uses an integrated bootstrap circuit with a rising under-voltage threshold of 12.1V typ and a falling threshold of 10.4V typ. |
| 7 | HIN(U) | input | U-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 8 | HIN(V) | input | V-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 9 | HIN(W) | input | W-phase high-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; control pulses shorter than the 1µs recommended minimum should be avoided. |
| 10 | LIN(U) | input | U-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 11 | LIN(V) | input | V-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 12 | LIN(W) | input | W-phase low-side gate driver input with positive logic and Schmitt-trigger thresholds compatible with LSTTL/CMOS down to 3.3V controller outputs; logic input voltage is limited to 0 to 5V. |
| 13 | VDD | power_in | Low-side control supply for input logic and output power stage; operation at power-on needs at least 12.1V typ, and all gate drivers shut down when VDD falls below 10.4V typ. |
| 14 | VFO | output | Fault output and direct NTC access referenced to VSS; it is an open-drain output that indicates VDD under-voltage or a triggered over-current at ITRIP and requires an external pull-up resistor. |
| 15 | ITRIP | input | Over-current shutdown input referenced to VSS with a comparator threshold of 400 to 540mV (470mV typ) and a typical 530ns input noise filter, shutting down all outputs after a typical 1000ns propagation delay. |
| 16 | VSS | power_in | Low-side control negative supply and reference ground for the input logic and the VFO/ITRIP thresholds. |
| 17 | NW | passive | W-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 18 | NV | passive | V-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 19 | NU | passive | U-phase low-side emitter available for phase current measurement; the connection to VSS should be kept as short as possible to avoid unnecessary inductive voltage drops. |
| 20 | W | output | Motor W-phase connection, forming the high-side emitter and low-side collector of the W leg. |
| 21 | V | power_in | Motor V-phase connection, forming the high-side emitter and low-side collector of the V leg. |
| 22 | U | output | Motor U-phase connection, forming the high-side emitter and low-side collector of the U leg. |
| 23 | P | power_in | Positive DC bus input to the high-side IGBTs; the bus voltage must not exceed 450V (surge limit 500V). |
| 24 | NC | unconnected | No connection. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | DIP-24 |
| Category | Power Management ICs |
| Pins | 24 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature range | Tstg | -40 | | 125 | °C | | 7 |
| Isolation test voltage | VISOL | 2000 | | | V | RMS, f = 60Hz, t = 1min | 7 |
| Operating case temperature range | TC | -40 | | 125 | °C | Refer to Figure 6 | 7 |
| Max. blocking voltage | VCES | 600 | | | V | IC = 250µA | 7 |
| DC link supply voltage of P-N | VPN | | | 450 | V | Applied between P-N | 7 |
| DC link supply voltage (surge) of P-N | VPN(surge) | | | 500 | V | Applied between P-N | 7 |
| Output current | IC | -15 | | 15 | A | TC = 25°C, TJ < 150°C | 7 |
| Maximum peak output current | IC(peak) | -30 | | 30 | A | TC = 25°C, less than 1ms | 7 |
| Short circuit withstand time | tSC | | | 5 | µs | VDC ≤ 400V, TJ = 150°C | 7 |
| Power dissipation per IGBT | Ptot | | | 58.6 | W | | 7 |
| Operating junction temperature range | TJ | -40 | | 150 | °C | | 7 |
| Single IGBT thermal resistance, junction-case | RthJC | | | 2.13 | K/W | | 7 |
| Single diode thermal resistance, junction-case | RthJCD | | | 3.42 | K/W | | 7 |
| Module supply voltage | VDD | -1 | | 20 | V | | 7 |
| High side floating supply voltage (VB vs. VS) | VBS | -1 | | 20 | V | | 7 |
| Input voltage LIN, HIN, ITRIP | VIN | -1 | | 10 | V | | 7 |
| Switching frequency | fPWM | | | 20 | kHz | | 7 |
| DC link supply voltage of P-N | VPN | 0 | | 400 | V | | 8 |
| High side floating supply voltage (VB vs. VS) | VBS | 13.5 | | 18.5 | V | | 8 |
| Low side supply voltage | VDD | 14.5 | 16 | 18.5 | V | | 8 |
| Control supply variation | ΔVBS | -1 | | 1 | V/µs | | 8 |
| Logic input voltages LIN, HIN, ITRIP | VIN | 0 | | 5 | V | | 8 |
| Between VSS - N (including surge) | VSS | -5 | | 5 | V | | 8 |
| Collector-Emitter saturation voltage | VCE(sat) | | 1.55 | 2.1 | V | IC = 10A, TJ = 25°C | 9 |
| Diode forward voltage | VF | | 1.75 | 2.45 | V | IF = 10A, TJ = 25°C | 9 |
| Collector-Emitter leakage current | ICES | | | 1 | mA | VCE = 600V | 9 |
| Logic "1" input voltage (LIN, HIN) | VIH | | 2.1 | 2.5 | V | | 9 |
| Logic "0" input voltage (LIN, HIN) | VIL | 0.7 | 0.9 | | V | | 9 |
| ITRIP positive going threshold | VIT,TH+ | 400 | 470 | 540 | mV | | 9 |
| ITRIP input hysteresis | VIT,HYS | 40 | 70 | | mV | | 9 |
| VDD supply under voltage positive going threshold | VDDUV+ | 10.8 | 12.1 | 13 | V | | 9 |
| VBS supply under voltage positive going threshold | VBSUV+ | 10.8 | 12.1 | 13 | V | | 9 |
| VDD supply under voltage negative going threshold | VDDUV- | 9.5 | 10.4 | 11.2 | V | | 9 |
| VBS supply under voltage negative going threshold | VBSUV- | 9.5 | 10.4 | 11.2 | V | | 9 |
| VDD supply under voltage lockout hysteresis | VDDUVH | 1 | 1.7 | | V | | 9 |
| VBS supply under voltage lockout hysteresis | VBSUVH | 1 | 1.7 | | V | | 9 |
| Quiescent VBx supply current (VBx only) | IQBS | | 300 | 500 | µA | HIN = 0V | 9 |
| Quiescent VDD supply current (VDD only) | IQDD | | 370 | 900 | µA | LIN = 0V, HINX = 5V | 9 |
| Input bias current | IIN+ | | 1 | 1.5 | mA | VIN = 5V | 9 |
| ITRIP input bias current | IITRIP+ | | 65 | 150 | µA | VITRIP = 5V | 9 |
| Fault clear time after ITRIP-fault | tFLTCLR | 40 | | | µs | VITRIP = 1V | 10 |
| Deadtime between low side and high side | DTPWM | 1.5 | | | µs | | 10 |
| Repetitive peak reverse voltage | VRRM | 600 | | | V | | 10 |
## CAD (KiCad official)
- Symbol: `IKCM15L60GD`
- Footprint: `Package_DIP:DIP-24_W7.62mm`
- 3D model: DIP-24 (KiCad packages3D, STEP)
- 3D model files: `ikcm15l60gd-etched.step` / `ikcm15l60gd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ikcm15l60gd.step` / `ikcm15l60gd.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Infineon Technologies datasheet](docs/ikcm15l60gd-datasheet.pdf) (17 pp, sha256 `40ab5e3310585958`, retrieved 2026-10-24, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ikcm15l60gd-datasheet.pdf)