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ICM7556ISD+T
Public Made by Adomby adom
Analog Devices Inc Maxim Integrated Timers / Counters, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownICM7556ISD+T
Analog Devices Inc Maxim Integrated · Timers / Counters · SOIC-14
ICM7556ISD+T from Analog Devices Inc Maxim Integrated, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DISCHARGE_A | passive | Section A discharge output that discharges the external timing capacitor when the output is low. |
| 2 | THRESHOLD_A | input | Section A threshold comparator input that resets the timer when above 2/3 of V+ (0.66 V+ typ at V+ = 5V). |
| 3 | CONTROL VOLTAGE_A | input | Section A control voltage input that sets the THRESHOLD and TRIGGER trip voltages and needs no decoupling capacitor. |
| 4 | RESET_A | input | Section A active-low reset input with trip voltage of about 0.7V that dominates all other inputs. |
| 5 | OUTPUT_A | output | Section A CMOS output that drives CMOS and TTL loads, sinking 3.2mA at 0.4V max low. |
| 6 | TRIGGER_A | input | Section A trigger input that sets the output high when below 1/3 of V+ (0.33 V+ typ at V+ = 5V). |
| 7 | GND | power_in | Ground, common to both timer sections. |
| 8 | TRIGGER_B | input | Section B trigger input that sets the output high when below 1/3 of V+ (0.33 V+ typ at V+ = 5V). |
| 9 | OUTPUT_B | output | Section B CMOS output that drives CMOS and TTL loads, sinking 3.2mA at 0.4V max low. |
| 10 | RESET_B | input | Section B active-low reset input with trip voltage of about 0.7V that dominates all other inputs. |
| 11 | CONTROL VOLTAGE_B | input | Section B control voltage input that sets the THRESHOLD and TRIGGER trip voltages and needs no decoupling capacitor. |
| 12 | THRESHOLD_B | input | Section B threshold comparator input that resets the timer when above 2/3 of V+ (0.66 V+ typ at V+ = 5V). |
| 13 | DISCHARGE_B | passive | Section B discharge output that discharges the external timing capacitor when the output is low. |
| 14 | V+ | power_in | Positive supply, 2V to 18V (absolute maximum +18V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices Inc Maxim Integrated |
| Package | SOIC-14 |
| Category | Clock/Timing |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | V+ | 2 | 16.5 | V | -20°C ≤ TA ≤ +85° | 4 | |
| Supply Voltage | V+ | 3 | 16 | V | -55°C ≤ TA ≤ +125° | 4 | |
| Supply Current ICM7556 | I+ | 60 | 500 | µA | V+ = 2V to 16.5V; TA = +25°C | 4 | |
| Supply Current ICM7556 | I+ | 240 | µA | V+ = 5V; TA = +25°C | 4 | ||
| Supply Current ICM7556 | I+ | 500 | µA | V+ = 5V; -20°C ≤ TA ≤ +85°C | 4 | ||
| Supply Current ICM7556 | I+ | 600 | µA | V+ = 5V; -55°C ≤ TA ≤ +125°C | 4 | ||
| Initial Accuracy (timing error) | 2 | 5 | % | Circuit of Figure 1b; RA = RB 100kΩ, C = 0.1µF, V+ = 5V | 4 | ||
| Drift with Temperature | 50 | ppm/°C | V+ = 5V | 4 | |||
| Drift with Temperature | 75 | ppm/°C | V+ = 10V | 4 | |||
| Drift with Temperature | 100 | ppm/°C | V+ = 15V | 4 | |||
| Drift with Supply Voltage | 1 | 3 | %V | V+ = 5V | 4 | ||
| Threshold Voltage | VTH | 0.63 | 0.66 | 0.67 | V+ | V+ = 5V | 4 |
| Trigger Voltage | VTRIG | 0.29 | 0.33 | 0.34 | V+ | V+ = 5V | 4 |
| Trigger Current | ITRIG | 50 | pA | V+ = 16.5V | 4 | ||
| Trigger Current | ITRIG | 10 | pA | V+ = 5V | 4 | ||
| Trigger Current | ITRIG | 1 | pA | V+ = 2V | 4 | ||
| Threshold Current | ITH | 50 | pA | V+ = 16.5V | 4 | ||
| Threshold Current | ITH | 10 | pA | V+ = 5V | 4 | ||
| Threshold Current | ITH | 1 | pA | V+ = 2V | 4 | ||
| Reset Current | IRST | 100 | pA | VREST = Ground; V+ = 16.5V | 4 | ||
| Reset Current | IRST | 20 | pA | VREST = Ground; V+ = 5V | 4 | ||
| Reset Current | IRST | 2 | pA | VREST = Ground; V+ = 2V | 4 | ||
| Reset Voltage | VRST | 0.4 | 0.7 | 1.2 | V | V+ = 16.5V | 5 |
| Control Voltage | VCV | 0.62 | 0.66 | 0.67 | V+ | V+ = 5V | 5 |
| Output Voltage Drop Output Lo | VO | 0.1 | 0.4 | V | V+ = 16.5V; ISINK = 3.2mA | 5 | |
| Output Voltage Drop Output Lo | VO | 0.15 | 0.4 | V | V+ = 5V; ISINK = 3.2mA | 5 | |
| Output Voltage Output Hi | VO | 15.75 | 16.25 | V | V+ = 16.5V; ISOURCE = 2.0mA | 5 | |
| Output Voltage Output Hi | VO | 4 | 4.5 | V | V+ = 5V; ISOURCE = 2.0mA | 5 | |
| Discharge Output Voltage | VDIS | 0.1 | 0.4 | V | V+ = 5V, IDIS = 3.2mA | 5 | |
| Rise Time of Output | tr | 40 | 75 | ns | RL = 10MΩ CL = 10pF V+ = 5V | 5 | |
| Fall Time of Output | tf | 40 | 75 | ns | RL = 10MΩ CL = 10pF V+ = 5V | 5 | |
| Guaranteed Max Oscillator Frequency | fmax | 500 | kHz | Astable Operation | 5 | ||
| Supply Voltage (absolute maximum) | V+ | 18 | V | Supply Voltage | 2 | ||
| Output Current | IOUT | 100 | mA | Output Current | 2 | ||
| Power Dissipation ICM7556 | PD | 300 | mW | ICM7556; below 125°C (Note 2) | 2 | ||
| Storage Temperature | TSTG | -65 | 150 | °C | Storage Temperature | 2 | |
| Lead Temperature (soldering, 60s) | 300 | °C | soldering, 60s | 2 | |||
| Operating Temperature Range (ICM7556ISD ordering range) | TA | -20 | 85 | °C | ICM7556ISD (14-pin SO) | 1 |
CAD (KiCad official)
- Symbol:
ICM7556ISD+T - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
icm7556isd-t-etched.step/icm7556isd-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);icm7556isd-t.step/icm7556isd-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices Inc Maxim Integrated datasheet (11 pp, sha256
30fd218015c11427, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).