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HVDA5425QDRQ1
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Texas Instruments CAN Transceivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HVDA5425QDRQ1
Texas Instruments · CAN Transceivers · SOIC-8
HVDA5425QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | CAN transmit data input: low for the dominant bus state and high for the recessive bus state; VIH is 0.7 × VIO to VIO and VIL is 0 to 0.3 × VIO (VIO = VCC on the -5 version). |
| 2 | GND | power_in | Ground connection; all voltages are referenced to this terminal. |
| 3 | VCC | power_in | Transceiver 5-V supply voltage, recommended 4.68 V to 5.33 V; decouple with a 100-nF ceramic capacitor close to the pin. |
| 4 | RXD | output | CAN receive data output that is low in the dominant bus state and high in the recessive bus state, with IOH limited to −2 mA and IOL to 2 mA recommended. |
| 5 | NC | unconnected | No connect on the HVDA54x-5 version because VIO is internally connected to VCC; the pin can be left floating or tied to any existing net. |
| 6 | CANL | bidirectional | Low-level CAN bus line; bus pins withstand −27 V to 40 V and have ±12 kV HBM ESD protection. |
| 7 | CANH | bidirectional | High-level CAN bus line; bus pins withstand −27 V to 40 V and have ±12 kV HBM ESD protection. |
| 8 | STB/S | input | Mode select, active high: STB selects standby mode on the HVDA540/541 and S selects silent mode on the HVDA542. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
HVDA5425QDRQ1 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
hvda5425qdrq1-etched.step/hvda5425qdrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hvda5425qdrq1.step/hvda5425qdrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (36 pp, sha256
9bd88dcc1a05e5fe, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HVDA5425QDRQ1
**Texas Instruments** · CAN Transceivers · SOIC-8
HVDA5425QDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | CAN transmit data input: low for the dominant bus state and high for the recessive bus state; VIH is 0.7 × VIO to VIO and VIL is 0 to 0.3 × VIO (VIO = VCC on the -5 version). |
| 2 | GND | power_in | Ground connection; all voltages are referenced to this terminal. |
| 3 | VCC | power_in | Transceiver 5-V supply voltage, recommended 4.68 V to 5.33 V; decouple with a 100-nF ceramic capacitor close to the pin. |
| 4 | RXD | output | CAN receive data output that is low in the dominant bus state and high in the recessive bus state, with IOH limited to −2 mA and IOL to 2 mA recommended. |
| 5 | NC | unconnected | No connect on the HVDA54x-5 version because VIO is internally connected to VCC; the pin can be left floating or tied to any existing net. |
| 6 | CANL | bidirectional | Low-level CAN bus line; bus pins withstand −27 V to 40 V and have ±12 kV HBM ESD protection. |
| 7 | CANH | bidirectional | High-level CAN bus line; bus pins withstand −27 V to 40 V and have ±12 kV HBM ESD protection. |
| 8 | STB/S | input | Mode select, active high: STB selects standby mode on the HVDA540/541 and S selects silent mode on the HVDA542. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `HVDA5425QDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `hvda5425qdrq1-etched.step` / `hvda5425qdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hvda5425qdrq1.step` / `hvda5425qdrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn65hvda540-q1) (36 pp, sha256 `9bd88dcc1a05e5fe`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hvda5425qdrq1-datasheet.pdf)