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HT82C251ANZ

HTCSEMI · CAN Transceivers · DIP-8

HT82C251ANZ from HTCSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input: a low level (~1 V) drives the bus dominant and a high level (~4 V) makes it recessive, with VIH of 0.7 VCC to VCC+0.3 V and VIL of -0.3 to 0.3 VCC.
2 GND power_in Ground reference pin for the transceiver; the datasheet specifies the RS slope resistor and mode selection are referenced to this ground.
3 VCC power_in Supply voltage input with a recommended range of 4.5 V to 5.5 V and an absolute maximum of 7.0 V.
4 RXD output Receive data output that is low when the bus is dominant and high when the bus is recessive, with VOH at least 0.8 VCC and VOL at most 0.2 VCC.
5 Vref power_in Reference voltage output equal to half of the supply voltage, specified as 0.45 VCC to 0.55 VCC at 1.0 V on pin 8 with
6 CANL bidirectional CAN low bus line whose dominant output voltage is 0.5 V to 2.0 V, with a bus input/output voltage range of -36 V to 36 V and short-circuit current limited to 200 mA.
7 CANH bidirectional CAN high bus line whose dominant output voltage is 3.0 V to 4.5 V, with a bus input/output voltage range of -36 V to 36 V and short-circuit current limited to 200 mA.
8 RS input Mode select pin: above 0.75 VCC selects standby, 0.4 to 0.6 VCC with an external resistor Rext selects reduced-RFI slope control, and below 0.3 VCC selects high-speed mode.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package DIP-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Pin 06, 07 transient voltage Vtr -200 200 V pins 06, 07 3
Storage temperature Tstg -60 150 °C 3
Junction temperature Tj 150 °C 3
Input/output high and low level voltage of CAN signal VCAN -36 36 V 3
Operating ambient temperature TA -40 150 °C stated as TA = -40 to 150C for all packages 1
Supply current, dominant I3 78 mA -40 ≤ Tamb ≤ +125 °C; dominant; V1 = 1,0 V, VCC < 5,1 V 4
Supply current, dominant I3 80 mA -40 ≤ Tamb ≤ +125 °C; dominant; V1 = 1,0 V, VCC < 5,25 V 4
Supply current, dominant I3 85 mA -40 ≤ Tamb ≤ +125 °C; dominant; V1 = 1,0 V, VCC < 5,5 V 4
Supply current, recessive I3 10 mA -40 ≤ Tamb ≤ +125 °C; recessive; V1 = 4,0 V, R8 = 47 kΩ 4
High-level input current IIH -200 30 μA 4,5 V < VCC < 5,5 V; V1 = 4,0 V 4
Low-level input current IIL -200 -100 μA 4,5 V < VCC < 5,5 V; V1 = 1,0 V 4
Recessive bus voltage V6,7 2 3 V 4,5 V < VCC < 5,5 V; V1 = 4,0 V, no load 4
Off-state output leakage current ILO -2 2 mA 4,5 V < VCC < 5,5 V; -2,0 V < (V6, V7) < 7,0 V 4
Off-state output leakage current ILO -10 10 mA 4,5 V < VCC < 5,5 V; -5,0 V < (V6, V7) < 36 V 4
CANH short-circuit current ISC7 -200 mA 4,5 V < VCC < 5,5 V; V7 = -5,0 V 5
CANL signal short-circuit current ISC6 200 mA 4,5 V < VCC < 5,5 V; V6 = 36 V 5
Differential input voltage (dominant mode) VDIFF(D) 1 5 V 4,5 V < VCC < 5,5 V; -7,0 V < (V6, V7) < 12 V 5
Low-level output voltage (pin 4) VOL 0 V 4,5 V < VCC < 5,5 V; I4 = 1,0 mA; max printed 0,2 VCC 5
CANL and CANH input resistance RI 5 25 kΩ 4,5 V < VCC < 5,5 V 5
Differential input resistance RDIFF 20 100 kΩ 4,5 V < VCC < 5,5 V 5
One bit transmitting minimum time tbit 1 μs RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 0 Ω 6
Input data transfer to active bus delay tonTXD 50 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 0 Ω 6
Input data transfer to inactive bus delay toffTXD 80 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 0 Ω 6
Input data transfer to active receiver delay tonRXD 120 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 0 Ω 6
Input data transfer to active receiver delay tonRXD 550 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 47 kΩ 6
Input data transfer to inactive receiver delay toffRXD 190 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 0 Ω 6
Input data transfer to inactive receiver delay toffRXD 400 ns RL = 60 Ω, CL = 100 pF; 4,5 V < VCC < 5,5 V; R8 = 47 kΩ 6
Wake-up time from standby mode (via 08 pin) tWAKE 20 μs 4,5 V < VCC < 5,5 V 6
Bus input data transfer delay to low on output of received data tdRXDL 3 μs 4,5 V < VCC < 5,5 V; V8 = 4,0 V 6
Input current for low RFI mode Islope -200 -10 μA 4,5 V < VCC < 5,5 V 6

CAD (KiCad official)

  • Symbol: HT82C251ANZ
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: ht82c251anz-etched.step / ht82c251anz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht82c251anz.step / ht82c251anz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (16 pp, sha256 55daffa5715e0cfc, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF