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Contents

README

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HT7705ARTZ

HTCSEMI · Analog To Digital Converters (ADCs) · TSSOP-16

HT7705ARTZ from HTCSEMI, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock Schmitt-triggered logic input used to access serial data, either a continuous clock or a noncontinuous clock.
2 MCLK IN input Master clock input for a crystal/resonator or CMOS-compatible external clock, operating in the range 500 kHz to 5 MHz.
3 MCLK OUT output Crystal/resonator connection or inverted clock output capable of driving one CMOS load, which can be turned off via the CLK DIS bit of the Clock Register.
4 CS input Active-low chip select logic input, which can be hard-wired low for three-wire interface mode or used as a frame synchronization signal.
5 RESET input Active-low logic input that resets control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status.
6 AIN2(+) input Positive input of differential analog input channel 2 on the HT7705.
7 AIN1(+) input Positive input of differential analog input channel 1 on the HT7705.
8 AIN1(-) input Negative input of differential analog input channel 1 on the HT7705.
9 REF IN(+) input Positive differential reference input, must be greater than REF IN(-) and can lie anywhere between VDD and GND.
10 REF IN(-) input Negative differential reference input, can lie anywhere between VDD and GND provided REF IN(+) is greater than REF IN(-).
11 AIN2(-) input Negative input of differential analog input channel 2 on the HT7705.
12 DRDY output Logic output where low indicates a new output word is available in the data register, also indicates completion of on-chip calibration.
13 DOUT output Serial data output from the output shift register, which can hold setup, communications, clock or data register information.
14 DIN input Serial data input to the input shift register, transferred to the setup, clock or communications register.
15 VDD power_in Supply voltage, +2.7 V to +5.25 V operation.
16 GND power_in Ground reference point for the internal circuitry.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Low Voltage VOL 0.4 V ISINK = 800 µA, VDD = 5 V, except MCLK OUT 3
Output High Voltage VOH 4 V ISOURCE = 200 µA, VDD = 5 V, except MCLK OUT 3
Floating State Leakage Current 10 µA 3
VDD Voltage (3 V range) VDD 2.7 3.3 V For specified performance 3
VDD Voltage (5 V range) VDD 4.75 5.25 V For specified performance 3
Supply Current, VDD 3 V IDD 0.32 mA BUF=0, fCLKIN=1 MHz, gains 1 to 128 3
Supply Current, VDD 3 V IDD 0.6 mA BUF=1, fCLKIN=1 MHz, gains 1 to 128 3
Supply Current, VDD 3 V IDD 0.4 mA BUF=0, fCLKIN=2.4576 MHz, gains 1 to 4 3
Supply Current, VDD 3 V IDD 0.7 mA BUF=1, fCLKIN=2.4576 MHz, gains 1 to 4 3
Supply Current, VDD 3 V IDD 1.1 mA BUF=1, fCLKIN=2.4576 MHz, gains 8 to 128 3
Supply Current, VDD 5 V IDD 0.45 mA BUF=0, fCLKIN=1 MHz, gains 1 to 128 3
Supply Current, VDD 5 V IDD 0.7 mA BUF=1, fCLKIN=1 MHz, gains 1 to 128 3
Supply Current, VDD 5 V IDD 0.6 mA BUF=0, fCLKIN=2.4576 MHz, gains 1 to 4 3
Supply Current, VDD 5 V IDD 0.85 mA BUF=0, fCLKIN=2.4576 MHz, gains 8 to 128 3
Supply Current, VDD 5 V IDD 0.9 mA BUF=1, fCLKIN=2.4576 MHz, gains 1 to 4 3
Supply Current, VDD 5 V IDD 1.3 mA BUF=1, fCLKIN=2.4576 MHz, gains 8 to 128 3
Standby (Power-Down) Current 16 µA External MCLK IN = 0 V or VDD, VDD = 5 V 3
Standby (Power-Down) Current 8 µA External MCLK IN = 0 V or VDD, VDD = 3 V 3
Master Clock Frequency fCLKIN 400 kHz Crystal oscillator or externally supplied 4
Master Clock Frequency fCLKIN 2.5 MHz For specified performance 4
Supply Voltage VDD -0.3 7 V VDD to GND, TA = +25°C 5
Analog Input Voltage to GND -0.3 V Max is VDD + 0.3 V 5
Reference Input Voltage to GND -0.3 V Max is VDD + 0.3 V 5
Digital Input Voltage to GND -0.3 V Max is VDD + 0.3 V 5
Digital Output Voltage to GND -0.3 V Max is VDD + 0.3 V 5
Operating Temperature Range -40 85 °C Commercial (B Version) 5
Storage Temperature Range -65 150 °C 5
Junction Temperature 150 °C 5
Package Power Dissipation 450 mW SSOP package 5
Thermal Impedance θJA 139 °C/W SSOP package 5
Lead Temperature, Vapor Phase 215 °C 60 sec 5
Lead Temperature, Infrared 220 °C 15 sec 5
ESD Rating 4000 V >4000 V 5
Floating State Output Capacitance 9 pF Sample tested at +25°C 3

CAD (KiCad official)

  • Symbol: HT7705ARTZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ht7705artz-etched.step / ht7705artz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht7705artz.step / ht7705artz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (33 pp, sha256 d1f222e90f7e8abb, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF