# HT7512ARMZ

**HTCSEMI** · Digital To Analog Converters (DACs) · MSOP-8

HT7512ARMZ from HTCSEMI, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input, operated from 2.7 V to 5.5 V in the specifications (the pin table says 2.5 V to 5.5 V), and should be decoupled to GND. |
| 2 | NC | unconnected | No internal connection. |
| 3 | NC | unconnected | No internal connection. |
| 4 | VOUT | output | Analog output voltage from the DAC, with a rail-to-rail output amplifier (0 V to VDD). |
| 5 | SYNC | input | Active-low level-triggered frame synchronization input that enables the input shift register; the DAC updates after the 16th clock unless SYNC is taken high before then, which interrupts and ignores the write. |
| 6 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz. |
| 7 | DIN | input | Serial data input to the 16-bit shift register, clocked in on the falling edge of the serial clock. |
| 8 | GND | power_in | Ground reference point for all circuitry on the part. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | MSOP-8 |
| Category | Data Converters |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy | INL | -16 |  | 16 | LSB | See Figure 5 | 3 |
| Differential Nonlinearity | DNL | -1 |  | 1 | LSB | Guaranteed monotonic by design (see Figure 6) | 3 |
| Zero-Code Error |  |  | 5 | 40 | mV | All zeroes loaded to DAC register (see Figure 9) | 3 |
| Full-Scale Error |  |  | -0.15 | -1.25 | % of FSR | All ones loaded to DAC register (see Figure 9) | 3 |
| Gain Error |  | -1.25 |  | 1.25 | % of FSR |  | 3 |
| Output Voltage Range |  | 0 |  | 5.5 | V | 0 to VDD | 3 |
| Output Voltage Settling Time |  |  | 8 | 10 | μs | 1/4 to 3/4 scale, RL = 2 kΩ, 0 pF < CL < 200 pF | 3 |
| Output Voltage Settling Time |  |  |  | 12 | μs | RL = 2 kΩ, CL = 500 pF | 3 |
| Input Current |  | -1 |  | 1 | μA |  | 3 |
| Input Low Voltage | VINL |  |  | 0.8 | V | VDD = 5 V | 3 |
| Input Low Voltage | VINL |  |  | 0.6 | V | VDD = 3 V | 3 |
| Input High Voltage | VINH | 2.4 |  |  | V | VDD = 5 V | 3 |
| Input High Voltage | VINH | 2.1 |  |  | V | VDD = 3 V | 3 |
| Supply Voltage | VDD | 2.7 |  | 5.5 | V |  | 3 |
| IDD (Normal Mode) | IDD |  | 140 | 250 | μA | VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND | 3 |
| IDD (Normal Mode) | IDD |  | 115 | 200 | μA | VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND | 3 |
| IDD (All Power-Down Modes) | IDD |  | 0.2 | 1 | μA | VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND | 3 |
| IDD (All Power-Down Modes) | IDD |  | 0.05 | 1 | μA | VDD = 2.7 V to 3.6 V, VIH = VDD and VIL = GND | 3 |
| SCLK cycle time (VDD 2.7 V to 3.6 V) | t1 | 50 |  |  | ns | VDD = 2.7 V to 3.6 V | 4 |
| SCLK cycle time (VDD 3.6 V to 5.5 V) | t1 | 33 |  |  | ns | VDD = 3.6 V to 5.5 V | 4 |
| SCLK high time | t2 | 13 |  |  | ns |  | 4 |
| SCLK low time (VDD 2.7 V to 3.6 V) | t3 | 22.5 |  |  | ns | VDD = 2.7 V to 3.6 V | 4 |
| SCLK low time (VDD 3.6 V to 5.5 V) | t3 | 13 |  |  | ns | VDD = 3.6 V to 5.5 V | 4 |
| SYNC to SCLK rising edge setup time | t4 | 0 |  |  | ns |  | 4 |
| Data setup time | t5 | 5 |  |  | ns |  | 4 |
| Data hold time | t6 | 4.5 |  |  | ns |  | 4 |
| SCLK falling edge to SYNC rising edge | t7 | 0 |  |  | ns |  | 4 |
| Minimum SYNC high time (VDD 2.7 V to 3.6 V) | t8 | 50 |  |  | ns | VDD = 2.7 V to 3.6 V | 4 |
| Minimum SYNC high time (VDD 3.6 V to 5.5 V) | t8 | 33 |  |  | ns | VDD = 3.6 V to 5.5 V | 4 |
| Zero-Code Error Drift |  |  | -20 |  | μV/°C |  | 3 |
| Gain Temperature Coefficient |  |  | -5 |  | ppm of FSR/°C |  | 3 |
| Slew Rate |  |  | 1 |  | V/μs |  | 3 |
| Capacitive Load Stability |  |  | 470 |  | pF | RL = ∞ | 3 |
| Capacitive Load Stability |  |  | 1000 |  | pF | RL = 2 kΩ | 3 |
| DC Output Impedance |  |  | 1 |  | Ω |  | 3 |
| Short Circuit Current |  |  | 50 |  | mA | VDD = 5 V | 3 |
| Short Circuit Current |  |  | 20 |  | mA | VDD = 3 V | 3 |
| Power-Up Time |  |  | 2.5 |  | μs | Coming out of power-down mode, VDD = 5 V | 3 |
| Power-Up Time |  |  | 5 |  | μs | Coming out of power-down mode, VDD = 3 V | 3 |
| Pin Capacitance |  |  | 3 |  | pF |  | 3 |
| Power Efficiency IOUT/IDD |  |  | 93 |  | % | ILOAD = 2 mA, VDD = 5 V | 3 |
| Operating temperature range | TA | -40 |  | 125 | °C | Ordering information, all packages | 1 |

## CAD (KiCad official)

- Symbol: `HT7512ARMZ`
- Footprint: `Package_SO:MSOP-8_3x3mm_P0.65mm`
- 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files: `ht7512armz-etched.step` / `ht7512armz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ht7512armz.step` / `ht7512armz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HTCSEMI datasheet](docs/ht7512armz-datasheet.pdf) (15 pp, sha256 `04e6ef7fe7ab918d`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ht7512armz-datasheet.pdf)