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HT74HC595ARZ

Public Made by Adom

by adom

HTCSEMI Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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HT74HC595ARZ

HTCSEMI · Shifting Register · SOIC-16

HT74HC595ARZ from HTCSEMI, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 QB tri_state Parallel data output QB. Noninverted, 3-state latch output driven by the second stage of the latch register. Disabled to high impedance when Output Enable (pin 13) is high.
2 QC tri_state Parallel data output QC. Noninverted, 3-state latch output driven by the third stage of the latch register. Disabled to high impedance when Output Enable is high.
3 QD tri_state Parallel data output QD. Noninverted, 3-state latch output driven by the fourth stage of the latch register. Disabled to high impedance when Output Enable is high.
4 QE tri_state Parallel data output QE. Noninverted, 3-state latch output driven by the fifth stage of the latch register. Disabled to high impedance when Output Enable is high.
5 QF tri_state Parallel data output QF. Noninverted, 3-state latch output driven by the sixth stage of the latch register. Disabled to high impedance when Output Enable is high.
6 QG tri_state Parallel data output QG. Noninverted, 3-state latch output driven by the seventh stage of the latch register. Disabled to high impedance when Output Enable is high.
7 QH tri_state Parallel data output QH. Noninverted, 3-state latch output driven by the eighth stage of the latch register. Disabled to high impedance when Output Enable is high.
8 GND power_in Ground reference (0 V). Common return for all logic and I/O.
9 SQH output Noninverted serial data output. Output of the eighth stage of the 8-bit shift register, used for cascading to the serial input of the next device. Not three-state capable.
10 Reset input Active-low, asynchronous shift-register reset input. A low on this pin resets the 8-bit shift register only; the 8-bit latch is not affected.
11 Shift Clock input Shift-register clock input. A low-to-high transition on this pin shifts the data at Serial Input A into the 8-bit shift register.
12 Latch Clock input Storage latch clock input. A low-to-high transition on this pin transfers the shift-register contents into the 8-bit latch register.
13 Output Enable input Active-low output enable. When low, latch data is presented at QA-QH. When high, QA-QH are forced into the high-impedance state. SQH is not affected by this control.
14 A input Serial data input. Data on this pin is shifted into the 8-bit serial shift register on the rising edge of Shift Clock.
15 QA tri_state Parallel data output QA. Noninverted, 3-state latch output driven by the first stage of the latch register. Disabled to high impedance when Output Enable (pin 13) is high.
16 VCC power_in Positive supply voltage. Recommended operating range 2.0 V to 6.0 V, absolute max 7.0 V referenced to GND.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • HT74HC595ARZ
  • HT74HC595ARZAN

CAD (KiCad official)

  • Symbol: HT74HC595ARZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ht74hc595arz-etched.step / ht74hc595arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht74hc595arz.step / ht74hc595arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (9 pp, sha256 2236b3ce4b6ba2d9, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF