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Ray Publish 0.1.0 5fa68d8 15d ago

HT7312ARTZ

HTCSEMI · Digital To Analog Converters (DACs) · SOT-23-6

HT7312ARTZ from HTCSEMI, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output Analog output voltage from the DAC; the output amplifier has rail-to-rail operation.
2 GND power_in Ground reference point for all circuitry on the part.
3 VDD power_in Power supply input, +2.7V to 5.5V.
4 DIN input Serial data input; data is clocked into the 16-bit input shift register on the falling edge of the serial clock input.
5 SCLK input Serial clock input; data can be transferred at rates up to 30MHz.
6 SYNC input Active-LOW level-triggered frame synchronization input that enables the input shift register; the DAC updates after the 16th clock unless SYNC is taken HIGH before then, which interrupts and ignores the write.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOT-23-6
Category ADC/DAC/Data Conversion
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD to GND VDD -0.3 6 V 2
Operating Temperature Range -40 105 °C 2
Storage Temperature Range -65 150 °C 2
Junction Temperature TJ max 150 °C 2
Thermal Impedance θJA 240 °C/W SOT23 package 2
Supply voltage VDD 2.7 5.5 V 3
IDD normal mode IDD 135 200 µA VDD = +3.6V to +5.5V; DAC active, excluding load current; VIH=VDD, VIL=GND 3
IDD normal mode IDD 115 160 µA VDD = +2.7V to +3.6V; VIH=VDD, VIL=GND 3
IDD all power-down modes IDD 0.2 1 µA VDD = +3.6V to +5.5V; VIH=VDD, VIL=GND 3
IDD all power-down modes IDD 0.05 1 µA VDD = +2.7V to +3.6V; VIH=VDD, VIL=GND 3
Resolution 12 Bits 3
Input Current -1 1 µA 3
VINH Input High Voltage VINH 2.4 V VDD = +5V 3
VINH Input High Voltage VINH 2.1 V VDD = +3V 3
VINL Input Low Voltage VINL 0.8 V VDD = +5V 3
VINL Input Low Voltage VINL 0.6 V VDD = +3V 3
Pin Capacitance 3 pF 3
Specified Performance temperature -40 105 °C 3
SCLK Cycle Time t1 50 ns VDD = 2.7V to 3.6V 4
SCLK Cycle Time t1 33 ns VDD = 3.6V to 5.5V 4
SCLK HIGH Time t2 13 ns VDD = 2.7V to 3.6V 4
SCLK LOW Time t3 22.5 ns VDD = 2.7V to 3.6V 4
SCLK LOW Time t3 13 ns VDD = 3.6V to 5.5V 4
SYNC to SCLK Rising Edge Setup Time t4 0 ns VDD = 2.7V to 3.6V 4
Data Setup Time t5 5 ns VDD = 2.7V to 3.6V 4
Data Hold Time t6 4.5 ns VDD = 2.7V to 3.6V 4
SCLK Falling Edge to SYNC Rising Edge t7 0 ns VDD = 2.7V to 3.6V 4
Minimum SYNC HIGH Time t8 50 ns VDD = 2.7V to 3.6V 4
Minimum SYNC HIGH Time t8 33 ns VDD = 3.6V to 5.5V 4
Power Efficiency IOUT/IDD 93 % ILOAD = 2mA, VDD = +5V 3

CAD (KiCad official)

  • Symbol: HT7312ARTZ
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: ht7312artz-etched.step / ht7312artz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht7312artz.step / ht7312artz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (14 pp, sha256 456896bf51bdacee, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF