# HT7135ARWZ

**HTCSEMI** · Analog To Digital Converters (ADC) · SOP-28-300mil

HT7135ARWZ from HTCSEMI, in a SOP-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC- | power_in | Negative supply, recommended -3 V to -8 V (-5 V nominal) relative to ground. |
| 2 | REF | input | Reference voltage input, positive with respect to ANLG COMMON, with Vref recommended at 1 V. |
| 3 | ANLG COMMON | passive | Analog common, connected to internal IN- during auto-zero, deintegrate and zero-integrator phases, and tied to the same point as IN- where possible. |
| 4 | INT OUT | output | Integrator output, connected to the integrating capacitor CINT (nominally 0.47 µF) and the rollover-correction diode. |
| 5 | AUTO ZERO | passive | Auto-zero capacitor connection (typically 1 µF) that compensates offset voltages of the buffer, integrator and comparator. |
| 6 | BUFF OUT | output | Buffer amplifier output, connected to the integrating resistor RINT. |
| 7 | Cref- | passive | Reference capacitor negative terminal (typically 1 µF). |
| 8 | Cref+ | passive | Reference capacitor positive terminal (typically 1 µF). |
| 9 | IN- | input | Differential analog input low, with input range from VCC- +1 V to VCC+ -0.5 V and typical leakage 1 pA. |
| 10 | IN+ | input | Differential analog input high, with input range from VCC- +1 V to VCC+ -0.5 V and typical leakage 1 pA. |
| 11 | VCC+ | power_in | Positive supply, 4 V to 6 V (5 V nominal). |
| 12 | D5 | output | Digit-drive output for the most significant digit, goes high for 200 clock pulses in the scan sequence. |
| 13 | B1 | output | Multiplexed BCD output bit 1 (LSB), TTL-compatible. |
| 14 | B2 | output | Multiplexed BCD output bit 2, TTL-compatible. |
| 15 | B4 | output | Multiplexed BCD output bit 4, TTL-compatible. |
| 16 | B8 | output | Multiplexed BCD output bit 8 (MSB), TTL-compatible. |
| 17 | D4 | output | Digit-drive output for the second digit, goes high for 200 clock pulses in the scan sequence. |
| 18 | D3 | output | Digit-drive output for the third digit, goes high for 200 clock pulses in the scan sequence. |
| 19 | D2 | output | Digit-drive output for the fourth digit, goes high for 200 clock pulses in the scan sequence. |
| 20 | D1 | output | Digit-drive output for the least significant digit, goes high for 200 clock pulses in the scan sequence. |
| 21 | BUSY | output | Goes high at the start of signal integrate and stays high until the first clock pulse after zero crossing, or until end of the cycle on over-range. |
| 22 | CLK | input | Clock input from 0 V to VCC+, with VIH 2.8 V min, VIL 0.8 V max and operating frequency up to 2 MHz. |
| 23 | POLARITY | output | Polarity output, high for a positive input signal, updated at the start of each deintegrate phase. |
| 24 | DGTL GND | power_in | Digital ground, whose return currents should not be sent to the analog ground line. |
| 25 | RUN/HOLD | input | When high or open, measurements run continuously every 40,002 clock pulses; when low, the reading is held, and a positive pulse over 300 ns starts a new cycle. |
| 26 | STROBE | output | Negative-going pulses transfer BCD data to external latches, UARTs or microprocessors, with the pulse low for 1/2 clock width. |
| 27 | OVER RANGE | output | Goes high after BUSY goes low at the end of a cycle when an over-range condition occurs. |
| 28 | UNDER RANGE | output | Goes high at the end of BUSY when the conversion is at or below 9% of full scale (count of 1800). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | SOP-28-300mil |
| Category | Data Acquisition |
| Pins | 28 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VCC+ | VCC+ | 4 | 5 | 6 | V |  | 3 |
| Supply voltage, VCC- | VCC- | -3 | -5 | -8 | V |  | 3 |
| High-level input voltage, CLK, RUN/HOLD | VIH | 2.8 |  |  | V | CLK, RUN/HOLD | 3 |
| Low-level input voltage, CLK, RUN/HOLD | VIL |  |  | 0.8 | V | CLK, RUN/HOLD | 3 |
| Maximum operating frequency, fclock | fclock |  | 1.2 | 2 | MHz | See Note 1 | 3 |
| Operating free-air temperature range, TA | TA | 0 |  | 70 | °C |  | 3 |
| Supply voltage (VCC+ with respect to VCC-) |  |  |  | 15 | V |  | 3 |
| Clock input voltage range |  | 0 |  |  | V |  | 3 |
| Operating free-air temperature range, TA | TA | 0 |  | 70 | °C |  | 3 |
| Storage temperature range, Tstg | Tstg | -65 |  | 150 | °C |  | 3 |
| High level output voltage D1-D5,B1,B2,B4,B8 | VOH | 2.4 |  | 5 | V | IO = -1 mA | 3 |
| High-level output voltage, other outputs | VOH | 4.9 |  | 5 | V | IO = -10 µA | 3 |
| Low-level output voltage | VOL |  |  | 0.4 | V | IO = 1.6 mA | 3 |
| Zero-reading temperature coefficient of output voltage | αVO |  | 0.5 | 2 | µV/°C | VID = 0, 0°C ≤ TA ≤ 70°C | 3 |
| High-level input current | IIH |  | 0.1 | 10 | µA | VI = 5 V, 0°C ≤ TA ≤ 70°C | 3 |
| Low-level input current | IIL |  | -0.02 | -0.1 | mA | VI = 0 V, 0°C ≤ TA ≤ 70°C | 3 |
| Input leakage current, IN- and IN+ | II |  | 1 | 10 | pA | VID = 0, TA = 25°C | 3 |
| Input leakage current, IN- and IN+ | II |  |  | 250 | pA | VID = 0, 0°C ≤ TA ≤ 70°C | 3 |
| Positive supply current | ICC+ |  | 1 | 2 | mA | fclock = 0, TA = 25°C | 3 |
| Positive supply current | ICC+ |  |  | 3 | mA | fclock = 0, 0°C ≤ TA ≤ 70°C | 3 |
| Negative supply current | ICC- |  | -0.8 | -2 | mA | fclock = 0, TA = 25°C | 3 |
| Negative supply current | ICC- |  |  | -3 | mA | fclock = 0, 0°C ≤ TA ≤ 70°C | 3 |
| Full-scale temperature coefficient | αFS |  |  | 5 | ppm/°C | VID = 2 V, 0°C ≤ TA ≤ 70°C | 4 |
| Full-scale symmetry error (rollover error) | EFS |  | 0.5 | 1 | count | VID = ±2 V | 4 |
| Display reading with 0-V input |  | 0 | 0 | 0 | Digital Reading | VID = 0, 0°C ≤ TA ≤ 70°C | 4 |
| Display reading in ratiometric operation |  | 0.9998 | 0.9999 | 1 | Digital Reading | VID = Vref, TA = 25°C | 4 |
| Display reading in ratiometric operation |  | 0.9995 | 0.9999 | 1.0005 | Digital Reading | VID = Vref, 0°C ≤ TA ≤ 70°C | 4 |

## CAD (KiCad official)

- Symbol: `HT7135ARWZ`
- Footprint: `Package_SO:SOP-28_8.4x18.16mm_P1.27mm`
- 3D model: SOP-28-300mil (KiCad packages3D, STEP)
- 3D model files: `ht7135arwz-etched.step` / `ht7135arwz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ht7135arwz.step` / `ht7135arwz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HTCSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588944595791462400) (12 pp, sha256 `b863401b8486350e`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ht7135arwz-datasheet.pdf)