component

HT7130-1

Public Made by Adom

by adom

UMW Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-89. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs ht7130-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
ht7130-1-etched.fit.json ht7130-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ht7130-1-etched.glb ht7130-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ht7130-1-etched.step ht7130-1: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ht7130-1.glb Publish 0.1.0 · Ray 1mo ago
ht7130-1.kicad_mod Publish 0.1.0 · Ray 1mo ago
ht7130-1.kicad_sym Publish 0.1.0 · Ray 1mo ago
ht7130-1.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 2 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
ht7130-1.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 11d ago
README.md ht7130-1: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 17d ago

HT7130-1

UMW · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-89

HT7130-1 from UMW, in a SOT-89. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the regulator. Common return for VIN and VOUT. Also the substrate/heat-sink tab connection on SOT-89.
2 VIN power_in Unregulated input supply. Absolute max 30 V; typical operating range ~4 V to 30 V for the 7130 variant. Bypass to GND with a 10 µF capacitor close to the pin.
3 VOUT power_out Regulated 3.0 V ±3% output (HT7130 variant), up to 100 mA. Dropout ~100 mV typical at 1 mA. Requires a 10 µF output capacitor to GND for stability.

Key specifications

Parameter Value
Manufacturer UMW
Package SOT-89
Category PMIC
Pins 3

CAD (KiCad official)

  • Symbol: HT7130-1
  • Footprint: Package_TO_SOT_SMD:SOT-89-3
  • 3D model: SOT-89 (KiCad packages3D, STEP)
  • 3D model files: ht7130-1-etched.step / ht7130-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht7130-1.step / ht7130-1.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ht7130-1.step 57 KB You want the bare part, or you mark your own boards.
ht7130-1-etched.step 909 KB You want the part with HT7130-1 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 265 faces against 42 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (14 pp, sha256 ae108c17cf1258c8, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF