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HT7050S

Public Made by Adom

by adom

UMW Supervisor and Reset ICs, SOT-23. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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HT7050S

UMW · Supervisor and Reset ICs · SOT-23

HT7050S from UMW, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output NMOS open-drain detector output. Pulls low when VDD falls below V_DET (~5.0V nominal for HT7050); external pull-up required. Rated sink current I_OL ≥ 4mA (typ 6mA) at V_OUT=0.2V with VDD=V_DET−0.2V. V_OUT range GND−0.3 to VDD+0.3.
3 VDD power_in Chip input / supply and monitored voltage. Operating range 1.5V to 12V, absolute maximum 15V. The internal comparator monitors this pin against the reference and asserts OUT low when VDD drops below V_DET (~5.0V for HT7050).
2 GND power_in Ground reference for the chip. Common return for VDD and OUT.

Key specifications

Parameter Value
Manufacturer UMW
Package SOT-23
Category PMIC
Pins 3

Ordering variants

Same part, different packaging or reel option.

  • HT7050SS

CAD (KiCad official)

  • Symbol: HT7050S
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ht7050s-etched.step / ht7050s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht7050s.step / ht7050s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (12 pp, sha256 ca4a5b03cf717e3e, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF