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HT651224BRSZ

Public Made by Adom

by adom

HTCSEMI LVDS ICs, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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HT651224BRSZ

HTCSEMI · LVDS ICs · SSOP-28-208mil

HT651224BRSZ from HTCSEMI, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVSS power_in Analog circuit ground.
2 RCLK_R/F input High selects an RCLK rising-edge data strobe, low selects an RCLK falling-edge data strobe.
3 REFCLK input Reference clock input for the internal PLL; a local clock must be applied to this pin for the deserializer to initialize.
4 AVDD power_in Analog circuit power supply, 3.0 V to 3.6 V (3.3 V typical).
5 RINP input Non-inverting LVDS differential receiver input, with a differential threshold of ±50 mV.
6 RINN input Inverting LVDS differential receiver input, with a differential threshold of ±50 mV.
7 PDB input Low puts the device into low-power mode, turns off the internal PLL and places DOUT0-DOUT9, RCLK and LOCK_B in high-impedance state; drive high to exit power-down.
8 NC unconnected No connection.
9 RCLK output Recovered clock output used to strobe DOUT0-DOUT9.
10 LOCK_B output Goes low when the internal PLL locks onto the embedded clock edge; high indicates loss of synchronization with outputs in high-impedance.
11 AVDD power_in Analog circuit power supply, 3.0 V to 3.6 V (3.3 V typical).
12 AVSS power_in Analog circuit ground.
13 AVSS power_in Analog circuit ground.
14 DVSS power_in Digital circuit ground.
15 DOUT9 output Parallel data output bit 9, strobed by RCLK.
16 DOUT8 output Parallel data output bit 8, strobed by RCLK.
17 DOUT7 output Parallel data output bit 7, strobed by RCLK.
18 DOUT6 output Parallel data output bit 6, strobed by RCLK.
19 DOUT5 output Parallel data output bit 5, strobed by RCLK.
20 DVSS power_in Digital circuit ground.
21 DVDD power_in Digital circuit power supply, 3.0 V to 3.6 V (3.3 V typical).
22 DVSS power_in Digital circuit ground.
23 DVDD power_in Digital circuit power supply, 3.0 V to 3.6 V (3.3 V typical).
24 DOUT4 output Parallel data output bit 4, strobed by RCLK.
25 DOUT3 output Parallel data output bit 3, strobed by RCLK.
26 DOUT2 output Parallel data output bit 2, strobed by RCLK.
27 DOUT1 output Parallel data output bit 1, strobed by RCLK.
28 DOUT0 output Parallel data output bit 0, strobed by RCLK.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SSOP-28-208mil
Category Interface
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage Supply Range 3 3.3 3.6 V 6
Receiver input voltage range 0 2.4 V 6
Supply noise voltage 100 mVP-P 6
Operating Temperature Range -40 25 85 °C 6
VDD to VSS -0.3 4 V 6
LVTTL input voltage -0.3 V upper limit printed as (VCC + 0.3), not numeric 6
LVTTL output voltage -0.3 V upper limit printed as (VCC + 0.3), not numeric 6
LVDS receiver input voltage -0.3 3.9 V 6
Electrostatic discharge (HBM) 4000 V HBM 6
Storage Temperature Range -60 150 °C 6
Operation Temperature Range -40 85 °C 6
Junction Temperature 150 °C 6
Low-level input voltage (deserializer LVCMOS/LVTTL) VIL 0.8 V 7
High-level input voltage (deserializer LVCMOS/LVTTL) VIH 2 V upper limit printed as VDD, not numeric 7
High-level output voltage VOH 3 V IOH = −5 mA; upper limit printed as VCC, not numeric 7
Low-level output voltage VOL 0.2 0.4 V IOL = 5 mA 7
Output short-circuit current (deserializer) IOS -15 -47 -80 mA VOUT = 0 V 7
High-impedance output current IOZ -10 1 10 uA 7
Differential threshold high voltage VTH 50 mV 7
Differential threshold low voltage VTL -50 mV 7
Input single-ended capacitance CI 0.5 pF 7
Input single-ended capacitance tolerance CI -20 20 % 7
Deserializer supply current, worst case (10 MHz) ICCR 15 35 mA f = 10 MHz, CL = 15 pF 7
Deserializer supply current, worst case (90 MHz) ICCR 80 95 mA f = 90 MHz, CL = 15 pF 7
Deserializer supply current, power down ICCXR 1 mA 7
REFCLK period tRFCP 11.1 100 ns 9
REFCLK duty cycle tRFDC 30 50 70 % 9
REFCLK input transition time tt(RF) 3 6 ns 9
REFCLK frequency tolerance -100 100 ppm 9
Receiver out clock period tRCP 11.1 100 ns tRCP = tTCP 9
Low-to-high transition time (ROUT0-ROUT9, LOCK_B, RCLK) tTLH(C) 1.2 2.5 ns 9
High-to-low transition time (ROUT0-ROUT9, LOCK_B, RCLK) tTHL(C) 1.2 2.5 ns 9
RCLK duty cycle tRDC 40 50 60 % 9

CAD (KiCad official)

  • Symbol: HT651224BRSZ
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: ht651224brsz-etched.step / ht651224brsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht651224brsz.step / ht651224brsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (14 pp, sha256 a3b87c36825ca569, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF