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HT651023BRSZ

Public Made by Adom

by adom

HTCSEMI LVDS ICs, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ht651023brszfactory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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HT651023BRSZ

HTCSEMI · LVDS ICs · SSOP-28-208mil

HT651023BRSZ from HTCSEMI, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection on the serializer.
2 SYNC input A pulse wider than 6 TCLK cycles on this input makes the serializer send 1026 SYNC patterns until SYNC goes low.
3 DIN0 input Parallel data input bit 0, latched by TCLK.
4 DIN1 input Parallel data input bit 1, latched by TCLK.
5 DIN2 input Parallel data input bit 2, latched by TCLK.
6 DIN3 input Parallel data input bit 3, latched by TCLK.
7 DIN4 input Parallel data input bit 4, latched by TCLK.
8 DIN5 input Parallel data input bit 5, latched by TCLK.
9 DIN6 input Parallel data input bit 6, latched by TCLK.
10 DIN7 input Parallel data input bit 7, latched by TCLK.
11 DIN8 input Parallel data input bit 8, latched by TCLK.
12 DIN9 input Parallel data input bit 9, latched by TCLK.
13 TCLK_R/F input High selects a TCLK rising-edge strobe and low selects a TCLK falling-edge data strobe.
14 TCLK input Reference clock input that drives the internal PLL and strobes parallel data into the latch; the clock rate must be 10 MHz to 90 MHz.
15 DVSS power_in Digital circuit ground.
16 DVSS power_in Digital circuit ground.
17 AVDD power_in Analog circuit power supply.
18 AVSS power_in Analog circuit ground.
19 DEN input High enables the serial data output; low puts the LVDS serial output into the high-impedance state.
20 AVSS power_in Analog circuit ground.
21 DON output Inverting LVDS differential output.
22 DOP output Non-inverting LVDS differential output.
23 AVSS power_in Analog circuit ground.
24 PDB input Low puts the device into a low-power mode, turns off the internal PLL and places the outputs into high-impedance state.
25 AVSS power_in Analog circuit ground.
26 AVDD power_in Analog circuit power supply.
27 DVDD power_in Digital circuit power supply.
28 DVDD power_in Digital circuit power supply.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SSOP-28-208mil
Category Communication Interface Chip/UART/485/232
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD to VSS VDD -0.3 4 V 6
LVDS receiver input voltage -0.3 3.9 V 6
LVDS driver output voltage -0.3 3.9 V 6
LVTTL input voltage -0.3 V 6
LVTTL output voltage -0.3 V 6
Storage Temperature Range -60 150 °C 6
Operation Temperature Range -40 85 °C 6
Junction Temperature 150 °C 6
Electrostatic discharge (HBM) 4000 V HBM 6
Voltage Supply Range 3 3.3 3.6 V 6
Receiver input voltage range 0 2.4 V 6
Supply noise voltage 100 mVP-P 6
Operating Temperature Range -40 25 85 °C 6
Low-level input voltage (serializer LVCMOS/LVTTL) VIL 0.8 V 7
High-level input voltage (serializer LVCMOS/LVTTL) VIH 2 V 7
Output differential voltage DOP-DON VOD 350 450 mV 7
Output differential voltage unbalance DVOD 35 mV 7
Offset voltage VOS 1.1 1.2 1.3 V 7
Offset voltage unbalance DVOS 5 35 mV 7
Output short circuit current IOS -90 -10 mA 7
Output single-ended capacitance CO 1 pF 7
Output single-ended capacitance tolerance CO -20 20 % 7
Serializer supply current, worst case ICCD 20 25 mA f = 10 MHz, RL = 27 Ω 7
Serializer supply current, worst case ICCD 50 55 mA f = 90 MHz, RL = 27 Ω 7
Serializer supply current, power down ICCXD 1 mA 7
Frequency tolerance (TCLK) -100 100 ppm 8
Transmit clock period tTCP 11.1 100 ns 8
TCLK input transition time tt(CLK) 3 6 ns 8
TCLK input jitter tJIT 150 ps(RMS) 8
LVDS low-to-high transition time tTLH(L) 0.2 0.4 ns RL = 27 Ω, CL = 10 9
LVDS high-to-low transition time tLTHL(L) 0.25 0.4 ns pF to VSS 9
DIN0-DIN9 setup to TCLK tSU(DI) 0.5 ns 9
DIN0-DIN9 hold from TCLK tH(DI) 4 ns 9
Deterministic jitter tDJIT 200 ps 9
Random jitter tRJIT 10 20 ps 9

CAD (KiCad official)

  • Symbol: HT651023BRSZ
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: ht651023brsz-etched.step / ht651023brsz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht651023brsz.step / ht651023brsz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (14 pp, sha256 a3b87c36825ca569, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF