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HT5615ARZ

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HTCSEMI Digital To Analog Converters (DAC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HT5615ARZ

HTCSEMI · Digital To Analog Converters (DAC) · SOP-8

HT5615ARZ from HTCSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DIN input Serial data input that is clocked into the 16-bit shift register most significant bit first while CS is low, with a minimum setup time of 45 ns before SCLK high and a minimum hold time of 0 ns.
2 SCLK input Serial clock input whose rising edge shifts data into the input register, with the maximum serial clock rate stated as approximately 14 MHz and SCLK to be held low when CS is high.
3 CS input Active-low chip select; the rising edge of CS transfers the shift register data to the DAC register, and CS transitions should occur only while SCLK is low, with a minimum CS pulse width high of 20 ns.
4 DOUT output Serial data output for daisy-chaining that presents the DIN data delayed by 16 clock cycles plus one clock width, with a propagation delay of 50 ns maximum at CL = 50 pF and a totem-pole output that does not go high-impedance.
5 AGND power_in Analog ground, which the datasheet recommends connecting directly to the system analog ground plane with negligible voltage drop and with the 0.1 µF VDD bypass returned to it.
6 REFIN input Buffered reference input with 10 MΩ input resistance and 5 pF input capacitance, operating from 0 V to VDD - 2 V, with a recommended reference voltage of 2 V to VDD - 2 V (2.048 V nominal) that sets the full-scale output.
7 OUT output DAC analog voltage output with a range of 0 V to VDD - 0.4 V at RL = 10 kΩ, equal to twice the reference voltage, and a buffer rated to drive a 2 kΩ load with 100 pF load capacitance.
8 VDD power_in Positive supply rated 4.5 V to 5.5 V (5 V nominal), with an absolute maximum of 7 V referenced to AGND.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOP-8
Category Data Acquisition
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VDD to AGND) VDD 7 V 3
Digital input voltage range to AGND -0.3 V Printed as -0.3 V to VDD + 0.3 V; upper limit is a formula, left null 3
Reference input voltage range to AGND -0.3 V Printed as -0.3 V to VDD + 0.3 V; upper limit is a formula, left null 3
Continuous current at any terminal 20 mA 3
Operating free-air temperature range (HT5615A) TA -40 85 °C HT5615A 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 260 °C 1,6 mm (1/16 inch) from case for 10 seconds 3
Supply voltage VDD 4.5 5 5.5 V 3
High-level digital input voltage VIH 2.4 V 3
Low-level digital input voltage VIL 0.8 V 3
Reference voltage, Vref to REFIN terminal Vref 2 2.048 V Maximum printed as VDD-2 V; formula, left null 3
Load resistance RL 2 kΩ 3
Operating free-air temperature (HT5615A) TA -40 85 °C HT5615A 3
Integral nonlinearity, end point adjusted (INL) INL 1 LSB Vref = 2.048V, See (1) 3
Differential nonlinearity (DNL) DNL 0.1 0.5 LSB Vref = 2.048V, See (2) 3
Zero-scale error (offset error at zero scale) EZS 3 LSB Vref = 2.048V, See (3) 3
Zero-scale-error temperature coefficient EZS TC 3 ppm/°C Vref = 2.048V, See (4) 3
Gain error EG 3 LSB Vref = 2.048V, See (5) 3
Gain-error temperature coefficient EG TC 1 ppm/°C Vref = 2.048V, See (6) 3
Power-supply rejection ratio, zero scale PSRR 80 dB Zero scale, See (7)(8) 3
Power-supply rejection ratio, gain PSRR 80 dB Gain, See (7)(8) 3
Voltage output range VO 0 V RL = 10k; maximum printed as VDD-0.4 V, formula, left null 4
Output load regulation accuracy 0.5 LSB VO(OUT) = 2V, RL = 2k 4
Output short circuit current IOSC 20 mA OUT to VDD or AGND 4
Output voltage, low-level VOL(low) 0.25 V IO(OUT) 5mA 4
Output voltage, high-level VOH(high) 4.75 V IO(OUT), 5mA 4
Reference input voltage VI 0 V Maximum printed as VDD-2 V, formula, left null 4
Reference input resistance ri 10 MΩ 4
High-level digital input voltage VIH 2.4 V DIN, SCLK, CS 4
Low-level digital input voltage VIL 0.8 V DIN, SCLK, CS 4
High-level digital input current IIH 1 µA VI = VDD 4
Low-level digital input current IIL 1 µA VI = 0 4
Digital output voltage, low-level VOL 0.4 V DOUT, IO = 2mA 4
Power supply current (Vref = 0) IDD 150 250 µA VDD = 5.5V, no load, Vref = 0, all inputs = 0V or VDD 4
Power supply current (Vref = 2.048V) IDD 230 350 µA VDD = 5.5V, no load, Vref = 2.048V, all inputs = 0V or VDD 4
Signal-to-noise + distortion S/(N+D) 60 dB Vref = 1VPP at 1kHz + 2.048Vdc, code = 11 1111 1111 4
Setup time, DIN before SCLK high tsu(DS) 45 ns 4
Hold time, DIN valid after SCLK high th(DH) 0 ns 4
Setup time, CS low to SCLK high tsu(CSS) 1 ns 4
Setup time, CS high to SCLK high tsu(CS1) 50 ns 4
Hold time, SCLK low to CS low th(CSH0) 1 ns 4
Hold time, SCLK low to CS high th(CSH1) 0 ns 4
Pulse duration, minimum chip select pulse width high tw(CS) 20 ns 4
Pulse duration, SCLK low tw(CL) 25 ns 4
Pulse duration, SCLK high tw(CH) 25 ns 4
Propagation delay time, DOUT tpd(DOUT) 50 ns CL = 50pF 4
Output slew rate SR 0.3 0.5 V/ms CL = 100pF, RL = 10kW, TA = +25°C 5
Output settling time ts 12.5 ms To 0.5LSB, CL = 100pF, RL = 10kW 5
Reference feedthrough -80 dB REFIN = 1VPP at 1kHz + 2.048Vdc 5
REFIN input capacitance Ci 5 pF Typically, independent of input code 9
Digital input capacitance Ci 8 pF DIN, SCLK, CS 4
Glitch energy 5 nV-s DIN = all 0s to all 1s 5
Reference input bandwidth (f-3dB) f-3dB 30 kHz REFIN = 0.2VPP + 2.048Vdc 5

CAD (KiCad official)

  • Symbol: HT5615ARZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ht5615arz-etched.step / ht5615arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht5615arz.step / ht5615arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (13 pp, sha256 fb5e8bb33b0e786e, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF