component

HT5320ARTZ

Public Made by Adom

by adom

HTCSEMI Digital To Analog Converters (DAC), SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionht5320artzfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ht5320artz / README.md
History Download
Ray Publish 0.1.0 275e8f9 7d ago

HT5320ARTZ

HTCSEMI · Digital To Analog Converters (DAC) · SOT-23-6

HT5320ARTZ from HTCSEMI, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT output Analog output voltage from the DAC, driven by a rail-to-rail output amplifier with an output range of 0 V to VDD.
2 GND power_in Ground reference point for all circuitry on the part, and the single ground return through which all digital and analog return currents must flow.
3 VDD power_in Power supply input from +2.7 V to 5.5 V, which also acts as the DAC reference because the part has no separate reference input.
4 DIN input Serial data input, clocked into the 16-bit input shift register on the falling edge of SCLK.
5 SCLK input Serial clock input for data transfer at rates up to 30 MHz.
6 SYNC input Active-LOW level-triggered frame sync input; the DAC updates after the 16th falling clock edge unless SYNC goes HIGH earlier, in which case the rising edge acts as an interrupt and the write is ignored.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOT-23-6
Category Data Acquisition
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -8 8 LSB 3
Differential Nonlinearity -1 1 LSB Tested Monotonic by Design 3
Zero Code Error 5 20 mV All Zeroes Loaded to DAC Register 3
Full-Scale Error -0.15 -1.25 % of FSR All Ones Loaded to DAC Register 3
Gain Error -1.25 1.25 % of FSR 3
Output Voltage Range 0 V Upper limit printed as VDD 3
Output Voltage Settling Time 8 10 µs 1/4 Scale to 3/4 Scale Change (400H to C00H); RL = 2k; 0pF < CL < 200pF 3
Capacitive Load Stability 1000 pF RL = 2k 3
Capacitive Load Stability 470 pF RL = × (as printed) 3
Input Current -1 1 µA 3
Input Low Voltage VINL 0.8 V VDD = +5V 3
Input Low Voltage VINL 0.6 V VDD = +3V 3
Input High Voltage VINH 2.4 V VDD = +5V 3
Input High Voltage VINH 2.1 V VDD = +3V 3
Supply Voltage VDD 2.7 5.5 V 3
IDD normal mode IDD 135 200 µA DAC Active and Excluding Load Current; VDD = +3.6V to +5.5V; VIH = VDD and VIL = GND 3
IDD normal mode IDD 115 160 µA DAC Active and Excluding Load Current; VDD = +2.7V to +3.6V; VIH = VDD and VIL = GND 3
IDD all power-down modes IDD 0.2 1 µA VDD = +3.6V to +5.5V; VIH = VDD and VIL = GND 3
IDD all power-down modes IDD 0.05 1 µA VDD = +2.7V to +3.6V; VIH = VDD and VIL = GND 3
Specified Performance Temperature Range -40 105 °C Specified Performance 3
VDD to GND VDD -0.3 6 V 2
Digital Input Voltage to GND -0.3 V Upper limit printed as VDD + 0.3 V 2
VOUT to GND VOUT -0.3 V Upper limit printed as VDD + 0.3 V 2
Operating Temperature Range -40 105 °C 2
Storage Temperature Range -65 150 °C 2
Junction Temperature Range (TJ max) TJ 150 °C 2
Lead Temperature, Soldering Vapor Phase 215 °C Vapor phase, 60s 2
Lead Temperature, Soldering Infrared 220 °C Infrared, 15s 2
SCLK Cycle Time t1 50 ns VDD = 2.7V to 3.6V 4
SCLK Cycle Time t1 33 ns VDD = 3.6V to 5.5V 4
SCLK High Time t2 13 ns VDD = 2.7V to 3.6V 4
SCLK Low Time t3 22.5 ns VDD = 2.7V to 3.6V 4
SCLK Low Time t3 13 ns VDD = 3.6V to 5.5V 4
SYNC to SCLK Rising Edge Setup Time t4 0 ns VDD = 2.7V to 3.6V 4
Data Setup Time t5 5 ns VDD = 2.7V to 3.6V 4
Data Hold Time t6 4.5 ns VDD = 2.7V to 3.6V 4
SCLK Falling Edge to SYNC Rising Edge t7 0 ns VDD = 2.7V to 3.6V 4
Minimum SYNC High Time t8 50 ns VDD = 2.7V to 3.6V 4
Minimum SYNC High Time t8 33 ns VDD = 3.6V to 5.5V 4
Zero Code Error Drift -20 µV/°C 3
Gain Temperature Coefficient -5 ppm of FSR/°C 3
Slew Rate 1 V/µs 3
Output Voltage Settling Time (RL=2k, CL=500pF) 12 µs RL = 2k; CL = 500pF 3
Code Change Glitch Impulse 20 nV-s 1LSB Change Around Major Carry 3
Digital Feedthrough 0.5 nV-s 3
DC Output Impedance 1 3
Short-Circuit Current 50 mA VDD = +5V 3
Short-Circuit Current 20 mA VDD = +3V 3
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = +5V 3
Power-Up Time 5 µs Coming out of power-down mode; VDD = +3V 3
Pin Capacitance 3 pF 3
Power Efficiency IOUT/IDD 93 % ILOAD = 2mA. VDD = +5V 3
JA Thermal Impedance (SOT23 package) JA 240 °C/W SOT23 package 2

CAD (KiCad official)

  • Symbol: HT5320ARTZ
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: ht5320artz-etched.step / ht5320artz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht5320artz.step / ht5320artz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (15 pp, sha256 f7460f35a9ff7f40, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF