component

HT5027

Public Made by Adom

by adom

HiTrend Tech (Shanghai) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersht5027factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

HT5027

HiTrend Tech (Shanghai) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

HT5027 from HiTrend Tech (Shanghai), in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OSCI input 32KHz clock (crystal) input.
2 PE.9/LVDIN1 bidirectional GPIO or external power-detect input LVDIN1 (compared against the 1.21V threshold).
3 PA.12/SEG35/ADCIN0 bidirectional GPIO, LCD SEG35 driver output, or external voltage sampling input 0 (ADCIN0).
4 PF.2/SFOUT/SEG48 bidirectional GPIO, energy pulse output (default apparent-energy pulse, configurable via EMCON) or LCD SEG48; output drive 5mA.
5 PF.1/QFOUT bidirectional GPIO or energy pulse output (default reactive-energy pulse, configurable via EMCON); output drive 5mA.
6 PF.0/PFOUT/TOUT3 bidirectional GPIO, energy pulse output (default active-energy pulse, configurable via EMCON) or second-pulse output TOUT3; output drive 5mA.
7 VREF power_out 1.185V metering reference voltage output; requires external 0.1uF and 1uF filter capacitors.
8 AVREG power_out 2.8V internal analog supply output; requires external 0.1uF and 10uF filter capacitors.
9 V1P input Current channel 1 analog input (positive), internal ESD protection, maximum signal ±800mVp.
10 V1N input Current channel 1 analog input (negative), internal ESD protection, maximum signal ±800mVp.
11 V2P input Current channel 2 analog input (positive), internal ESD protection, maximum signal ±800mVp.
12 V2N input Current channel 2 analog input (negative), internal ESD protection, maximum signal ±800mVp.
13 V3P input Voltage channel analog input (positive), internal ESD protection, maximum signal ±800mVp.
14 V3N input Voltage channel analog input (negative), internal ESD protection, maximum signal ±800mVp.
15 AVSS power_in Analog ground.
16 PA.7/INT2/SEG33 bidirectional High-current GPIO (30mA drive), external interrupt input INT2 (2us filter) or LCD SEG33 output.
17 PB.0/SEG0 bidirectional GPIO or LCD SEG0 driver output.
18 PB.1/SEG1 bidirectional GPIO or LCD SEG1 driver output.
19 PB.2/SEG2/VLCD0 bidirectional GPIO, LCD SEG2 output, or LCD resistor-divider bias voltage output VLCD0 (needs external 0.47uF capacitor).
20 PB.3/SEG3/VLCD1 bidirectional GPIO, LCD SEG3 output, or LCD resistor-divider bias voltage output VLCD1 (needs external 0.47uF capacitor).
21 PB.4/SEG4/VLCD2 bidirectional GPIO, LCD SEG4 output, or LCD resistor-divider bias voltage output VLCD2 (needs external 0.47uF capacitor).
22 PB.5/SEG5/VLCD3 bidirectional GPIO, LCD SEG5 output, or LCD resistor-divider bias voltage output VLCD3 (needs external 0.47uF capacitor).
23 PB.6/SEG6 bidirectional GPIO or LCD SEG6 driver output.
24 VDD1P5 power_out Internal 1.5V output; requires external 0.1uF filter capacitor.
25 GND power_in Ground (listed as analog ground).
26 PB.7/SEG7 bidirectional GPIO or LCD SEG7 driver output.
27 PA.6/INT1/SCANIN1/JTAGWDTEN bidirectional High-current GPIO (30mA drive), external interrupt INT1 (2us filter), keyscan column input SCANIN1; as JTAGWDTEN, debug mode is entered when TEST and this pin are both low.
28 TEST input Test pin with 2us filter; test mode is entered if it goes low before JTAGWDTEN.
29 PB.12/SEG12/INT8 bidirectional GPIO, LCD SEG12 output, or external interrupt input INT8.
30 PB.13/SEG13/SWIO bidirectional GPIO, LCD SEG13 output, or debug-mode SW data signal SWIO (default function after power-up).
31 PB.14/SEG14/INT9 bidirectional GPIO, LCD SEG14 output, or external interrupt input INT9.
32 PB.15/SEG15/SWCLK bidirectional GPIO, LCD SEG15 output, or debug-mode SW clock signal SWCLK (default function after power-up).
33 PD.14/COM6/SEG26 bidirectional GPIO, LCD COM6, or LCD SEG26 driver output.
34 PD.15/COM7/SEG27 bidirectional GPIO, LCD COM7, or LCD SEG27 driver output.
35 PE.1/TX4/TOUT2 bidirectional GPIO, UART4 transmit, or second-pulse output TOUT2; output drive 5mA.
36 PE.2/RX4/7816_0 bidirectional GPIO, UART4 receive, or 7816 port 0.
37 PE.3/CLKOUT/SEG53 bidirectional GPIO, internal divided clock output (ESAM/CARD clock), or LCD SEG53 output.
38 PE.4/RX3/7816_1 bidirectional GPIO, UART3 receive, or 7816 port 1.
39 PE.5/TX3/SEG49 bidirectional GPIO, UART3 transmit, or LCD SEG49 output.
40 PC.8/TOUT1/INT7 bidirectional GPIO, second-pulse output 1 (TOUT1), or external interrupt input INT7.
41 DGND power_in Chip digital ground.
42 VDD power_in Internal power input supplying the internal digital supply; must be externally connected to the other VDD pin.
43 PA.3/SEG31 bidirectional GPIO or LCD SEG31 driver output.
44 PD.5/SEG21/SCANOUT3 bidirectional GPIO, LCD SEG21 output, or keyscan row output SCANOUT3; output drive 5mA.
45 PD.4/SEG20/SCANOUT2 bidirectional GPIO, LCD SEG20 output, or keyscan row output SCANOUT2; output drive 5mA.
46 PD.3/SEG19/SCANOUT1 bidirectional GPIO, LCD SEG19 output, or keyscan row output SCANOUT1; output drive 5mA.
47 PD.2/SEG18/SCANOUT0 bidirectional GPIO, LCD SEG18 output, or keyscan row output SCANOUT0; output drive 5mA.
48 /RST input Active-low reset input with 2us filter; a low pulse wider than 2us resets the chip.
49 PA.8/INT3/SEG34 bidirectional High-current GPIO (30mA drive), external interrupt input INT3 (2us filter) or LCD SEG34 output.
50 PC.3/TX0/SEG46 bidirectional GPIO, UART0 transmit, or LCD SEG46 output.
51 PC.2/RX0/SEG45 bidirectional GPIO, UART0 receive, or LCD SEG45 output.
52 PD.13/COM5/SEG25 bidirectional GPIO, LCD COM5, or LCD SEG25 driver output.
53 PD.12/COM4/SEG24 bidirectional GPIO, LCD COM4, or LCD SEG24 driver output.
54 PD.11/COM3 bidirectional GPIO or LCD COM3 driver output.
55 PD.10/COM2 bidirectional GPIO or LCD COM2 driver output.
56 PD.9/COM1 bidirectional GPIO or LCD COM1 driver output.
57 PD.8/COM0 bidirectional GPIO or LCD COM0 driver output.
58 PA.5/INT0/SCANIN0 bidirectional GPIO, external interrupt input INT0 (2us filter), or keyscan column input SCANIN0.
59 VBAT power_in Battery supply input.
60 VSYS power_in System power supply input.
61 VDD power_out System power output; must be externally connected to the other VDD pin.
62 GND power_in Ground (listed as analog ground).
63 PE.7/LVDIN0/SEG47 bidirectional GPIO, external power-detect input LVDIN0, or LCD SEG47 output.
64 OSCO output External low-frequency clock (crystal) drive output.

Key specifications

Parameter Value
Manufacturer HiTrend Tech (Shanghai)
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VCC 2.2 3.3 5.5 V Voltage on input supply pin 299
High-level input voltage (Reset, TEST) Vih1 0.8 VCC Reset pin, TEST pin 299
High-level input voltage (PC9,PC10,PE0,PE3,PE6) Vih2 0.6 VCC PC9,PC10,PE0,PE3,PE6 299
High-level input voltage (other pins) Vih3 0.7 VCC All pins except power, ground, Reset, TEST, PC9, PC10, PE0, PE3, PE6 299
Low-level input voltage Vil 0.2 VCC All pins except power and ground 299
Supply voltage (limit table) VCC 2.2 5.5 V Voltage on input supply pin 300
Digital input voltage Vi 0 5.5 V All digital pins 300
ADC input limit voltage Via 0 3 V ADC pin input voltage; above this the pin may be damaged 300
VBAT input limit voltage Vib 0 5 V VBAT pin input voltage; above this the pin may be damaged 300
Input current Idd 50 mA VCC supply pin 300
Ground current Iss 50 mA All GND pins 300
Storage temperature Tstg -65 150 ℃ Chip limit storage temperature 300
ESD (HBM), ADC input pins Vesd -6000 6000 V ADC input pins 300
ESD (HBM), all pins Vesd -8000 8000 V All chip pins 300
Operating voltage range 2.2 5.5 V 10
Operating temperature range -40 85 ℃ 10
Internal reference voltage temperature coefficient -10 10 ppm/℃ On-chip reference 1.2V 11
Hold mode power consumption at -45℃ 2.2 uA 3.3V supply, Hold mode, -45℃ 300
Hold mode power consumption at room temperature 3.9 uA 3.3V supply, Hold mode, room temperature 300
Hold mode power consumption at 85℃ 34.3 uA 3.3V supply, Hold mode, 85℃ 300
Sleep mode power consumption at -45℃ 1.9 uA 3.3V supply, Sleep mode, -45℃ 301
Sleep mode power consumption at room temperature 2.9 uA 3.3V supply, Sleep mode, room temperature 301
Sleep mode power consumption at 85℃ 16 uA 3.3V supply, Sleep mode, 85℃ 301
HRC module power consumption 116 uA 3.3V supply 301
LRC module power consumption 0.9 uA 3.3V supply 301
PLL module power consumption 205 uA 3.3V supply 301

CAD (KiCad official)

  • Symbol: HT5027
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ht5027-etched.step / ht5027-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht5027.step / ht5027.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HiTrend Tech (Shanghai) datasheet (307 pp, sha256 1116db0452f89da9, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF