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HT5017

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HiTrend Tech (Shanghai) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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HT5017

HiTrend Tech (Shanghai) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

HT5017 from HiTrend Tech (Shanghai), in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OSCI input External low-frequency 32 kHz clock input.
2 PE.9/LVDIN1 bidirectional GPIO PE.9 or LVDIN1 external power-detect input (threshold 1.21V).
3 PA.12/SEG35/ADCIN0 bidirectional GPIO PA.12, LCD SEG35, or external voltage sampling input 0 (ADCIN0) with 2us filter.
4 PF.2/SFOUT bidirectional GPIO PF.2 or apparent-energy pulse output SFOUT by default, 5mA drive, other pulse types selectable via EMCON.
5 PF.1/QFOUT bidirectional GPIO PF.1 or reactive-energy pulse output QFOUT by default, 5mA drive, other pulse types selectable via EMCON.
6 PF.0/PFOUT bidirectional GPIO PF.0 or active-energy pulse output PFOUT by default, 5mA drive, other pulse types selectable via EMCON.
7 VREF power_in 1.185V metering reference voltage output, requires external 0.1uF and 1uF filter capacitors.
8 AVREG power_out 2.8V internal analog supply output, requires external 0.1uF and 10uF filter capacitors.
9 V1P input Current channel 1 analog input (positive), internal ESD protection, max signal ±800mVp.
10 V1N input Current channel 1 analog input (negative), internal ESD protection, max signal ±800mVp.
11 V2P input Current channel 2 analog input (positive), internal ESD protection, max signal ±800mVp.
12 V2N input Current channel 2 analog input (negative), internal ESD protection, max signal ±800mVp.
13 V3P input Voltage channel analog input (positive), internal ESD protection, max signal ±800mVp.
14 V3N input Voltage channel analog input (negative), internal ESD protection, max signal ±800mVp.
15 AVSS power_in Analog ground.
16 PA.7/INT2/SEG33 bidirectional GPIO PA.7, external interrupt INT2 or LCD SEG33, 2us filter, 30mA output drive.
17 PB.0/SEG0 bidirectional GPIO PB.0 or LCD segment SEG0.
18 PB.1/SEG1 bidirectional GPIO PB.1 or LCD segment SEG1.
19 PB.2/SEG2 bidirectional GPIO PB.2 or LCD segment SEG2.
20 PB.3/SEG3 bidirectional GPIO PB.3 or LCD segment SEG3.
21 PB.4/SEG4 bidirectional GPIO PB.4 or LCD segment SEG4.
22 PB.5/SEG5 bidirectional GPIO PB.5 or LCD segment SEG5.
23 PB.6/SEG6 bidirectional GPIO PB.6 or LCD segment SEG6.
24 VDD1P5 power_out Internal 1.5V output, requires external 0.1uF filter capacitor.
25 GND power_in Ground (listed as analog ground).
26 PB.7/SEG7 bidirectional GPIO PB.7 or LCD segment SEG7.
27 PA.6/INT1/SCANIN1/JTAGWDTEN bidirectional GPIO PA.6, INT1, keyscan input SCANIN1 or JTAGWDTEN (when TEST=0), 2us filter, 30mA output drive, internal constant pull-up.
28 TEST input Test pin with 2us filter and internal constant pull-up.
29 PB.12/SEG12 bidirectional GPIO PB.12 or LCD segment SEG12.
30 PB.13/SEG13/SWIO bidirectional GPIO PB.13, LCD SEG13, or SW debug data I/O (SWIO).
31 PB.14/SEG14 bidirectional GPIO PB.14 or LCD segment SEG14.
32 PB.15/SEG15/SWCLK bidirectional GPIO PB.15, LCD SEG15, or SW debug clock (SWCLK).
33 PD.14/COM6/SEG26 bidirectional GPIO PD.14, LCD COM6 or SEG26.
34 PD.15/COM7/SEG27 bidirectional GPIO PD.15, LCD COM7 or SEG27.
35 PE.1/TX4/TOUT2 bidirectional GPIO PE.1, UART TX4 transmit or seconds pulse output TOUT2, 5mA output drive.
36 PE.2/RX4/7816_0 bidirectional GPIO PE.2, UART RX4 receive or 7816_0, 2us filter.
37 PE.3/CLKOUT bidirectional GPIO PE.3 or CLKOUT clock output (ESAM/CARD_CLK).
38 PE.4/RX3/7816_1 bidirectional GPIO PE.4, UART RX3 receive or 7816 function, 2us filter.
39 PE.5/TX3 bidirectional GPIO PE.5 or UART3 transmit TX3.
40 PC.8/TOUT1 bidirectional GPIO PC.8 or seconds pulse output 1 (TOUT1).
41 DGND power_in Chip digital ground.
42 VDD power_in Internal supply input, must be connected externally to the other VDD pin to supply the internal digital supply.
43 PA.3/SEG31 bidirectional GPIO PA.3 or LCD segment SEG31.
44 PD.5/SEG21/SCANOUT3 bidirectional GPIO PD.5, LCD SEG21 or keyscan output SCANOUT3, 5mA output drive.
45 PD.4/SEG20/SCANOUT2 bidirectional GPIO PD.4, LCD SEG20 or keyscan output SCANOUT2, 5mA output drive.
46 PD.3/SEG19/SCANOUT1 bidirectional GPIO PD.3, LCD SEG19 or keyscan output SCANOUT1, 5mA output drive.
47 PD.2/SEG18/SCANOUT0 bidirectional GPIO PD.2, LCD SEG18 or keyscan output SCANOUT0, 5mA output drive.
48 /RST input Active-low reset input with 2us filter (pulses narrower than 2us do not reset) and internal constant pull-up.
49 PA.8/INT3/SEG34 bidirectional GPIO PA.8, external interrupt INT3 or LCD SEG34, 2us filter, 30mA output drive.
50 PC.3/TX0 bidirectional GPIO PC.3 or UART0 transmit TX0.
51 PC.2/RX0 bidirectional GPIO PC.2 or UART0 receive RX0, 2us filter.
52 PD.13/COM5/SEG25 bidirectional GPIO PD.13, LCD COM5 or SEG25.
53 PD.12/COM4/SEG24 bidirectional GPIO PD.12, LCD COM4 or SEG24.
54 PD.11/COM3 bidirectional GPIO PD.11 or LCD COM3.
55 PD.10/COM2 bidirectional GPIO PD.10 or LCD COM2.
56 PD.9/COM1 bidirectional GPIO PD.9 or LCD COM1.
57 PD.8/COM0 bidirectional GPIO PD.8 or LCD COM0.
58 PA.5/INT0/SCANIN0 bidirectional GPIO PA.5, external interrupt INT0 or keyscan input SCANIN0, 2us filter.
59 VBAT power_in Battery supply input (input limit 3.6V; VBAT range 1V to 3.6V).
60 VSYS power_in System power supply input.
61 VDD power_out System power output (switched from VSYS or VBAT); must be connected externally to the other VDD pin.
62 GND power_in Ground (listed as analog ground).
63 PE.7/LVDIN0 bidirectional GPIO PE.7 or LVDIN0 external power-detect input (threshold 1.21V).
64 OSCO output External low-frequency crystal drive output.

Key specifications

Parameter Value
Manufacturer HiTrend Tech (Shanghai)
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VCC 2.2 3.3 5.5 V Voltage on input supply pin 256
High-level input voltage (Reset, TEST) Vih 0.8 VCC Reset pin, TEST pin; printed 0.8VCC 256
High-level input voltage (PC9,PC10,PE0,PE3,PE6) Vih 0.6 VCC PC9,PC10,PE0,PE3,PE6; printed 0.6VCC 256
High-level input voltage (all other pins) Vih 0.7 VCC All pins except power, ground, Reset, TEST, PC9, PC10, PE0, PE3, PE6; printed 0.7VCC 256
Low-level input voltage Vih 0.2 VCC All pins except power and ground; printed 0.2VCC 256
High-level output current (PA.6,PA.7,PA.8,PC.0) Ioh 10 mA VCC=3.3V, Vio drops to 0.9VCC 256
Low-level output current (PA.6,PA.7,PA.8,PC.0) Iol 20 mA VCC=3.3V, Vio rises to 0.1VCC 256
High-level output current (PD.4-7, PC.5-11, PE.1) Ioh 5 mA VCC=3.3V, Vio drops to 0.9VCC 256
Low-level output current (PD.4-7, PC.5-11, PE.1) Iol 5 mA VCC=3.3V, Vio drops to 0.9VCC 257
High-level output current (other pins) Ioh 3 mA VCC=3.3V, Vio drops to 0.9VCC; all except PA.6,PA.7,PA.8,PC.0,PD.4-7,PC.5-11,PE.1 257
Low-level output current (other pins) Iol 3 mA VCC=3.3V, Vio drops to 0.9VCC; all except PA.6,PA.7,PA.8,PC.0,PD.4-7,PC.5-11,PE.1 257
Input supply voltage (limit) VCC 2.2 5.5 V Voltage on input supply pin 257
Input voltage Vi 0 5.5 V All digital pins 257
ADC input limit voltage Via 0 1.5 V ADC pin input voltage; higher may damage the pin 257
VBAT input limit voltage Vib 0 3.6 V VBAT pin input voltage; higher may damage the pin 257
Input current Idd 50 mA VCC supply pin 257
Ground current Iss 50 mA All GND pins 257
Storage temperature Tstg -65 150 °C Chip limit storage temperature 258
Static ESD (HBM), ADC input pins Vesd -6000 6000 V ADC input pins 258
Static ESD (HBM), all chip pins Vesd -8000 8000 V All chip pins 258
Operating voltage range 2 5.5 V 10
Operating temperature range -40 85 ℃ 10
Hold mode minimum power consumption 3.7 uA 3.3V supply 258
Sleep mode minimum power consumption 2.9 uA 3.3V supply 258
Current at 32768Hz with LCD on 48 uA 3.3V supply, low frequency 32768Hz, LCD enabled 258
Current, PLL 39.32M CPU, all digital modules on 7.34 mA 3.3V supply, PLL clock, CPU at 39.32M, all digital modules on 258

CAD (KiCad official)

  • Symbol: HT5017
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ht5017-etched.step / ht5017-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht5017.step / ht5017.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HiTrend Tech (Shanghai) datasheet (262 pp, sha256 ca455c807ac53a76, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF