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HT4093ARZ

Public Made by Adom

by adom

HTCSEMI Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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HT4093ARZ

HTCSEMI · Flip Flops · SOIC-14

HT4093ARZ from HTCSEMI, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN 1A input Input 1 of Schmitt-trigger NAND gate A; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
2 IN 2A input Input 2 of Schmitt-trigger NAND gate A; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
3 OUTA output Output of NAND gate A; Vout must stay within VSS to VDD, and unused outputs must be left open.
4 OUTB output Output of NAND gate B; Vout must stay within VSS to VDD, and unused outputs must be left open.
5 IN 1B input Input 1 of Schmitt-trigger NAND gate B; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
6 IN 2B input Input 2 of Schmitt-trigger NAND gate B; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
7 VSS power_in Ground/negative supply reference; all voltages are referenced to VSS.
8 IN 1C input Input 1 of Schmitt-trigger NAND gate C; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
9 IN 2C input Input 2 of Schmitt-trigger NAND gate C; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
10 OUTC output Output of NAND gate C; Vout must stay within VSS to VDD, and unused outputs must be left open.
11 OUTD output Output of NAND gate D; Vout must stay within VSS to VDD, and unused outputs must be left open.
12 IN 1D input Input 1 of Schmitt-trigger NAND gate D; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
13 IN 2D input Input 2 of Schmitt-trigger NAND gate D; unused inputs must be tied to an appropriate logic level (VSS or VDD), never left floating.
14 VDD power_in Positive supply; the datasheet rates VDD at 3.0 Vdc to 18 Vdc (absolute maximum −0.5 to +18.0 V with respect to VSS).

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage '0' Level VOL 0.05 Vdc VDD 5.0 Vdc; Vin = VDD or 0; TA 25°C 3
Output Voltage '1' Level VOH 4.95 Vdc VDD 5.0 Vdc; Vin = 0 or VDD; TA 25°C 3
Output Voltage '1' Level VOH 9.95 Vdc VDD 10 Vdc; Vin = 0 or VDD; TA 25°C 3
Output Voltage '1' Level VOH 14.95 Vdc VDD 15 Vdc; Vin = 0 or VDD; TA 25°C 3
Output Drive Current, Source IOH -2.4 mAdc VDD 5.0 Vdc; VOH = 2.5 Vdc; TA 25°C 3
Output Drive Current, Source IOH -0.51 mAdc VDD 5.0 Vdc; VOH = 4.6 Vdc; TA 25°C 3
Output Drive Current, Source IOH -1.3 mAdc VDD 10 Vdc; VOH = 9.5 Vdc; TA 25°C 3
Output Drive Current, Source IOH -3.4 mAdc VDD 15 Vdc; VOH = 13.5 Vdc; TA 25°C 3
Output Drive Current, Sink IOL 0.51 mAdc VDD 5.0 Vdc; VOL = 0.4 Vdc; TA 25°C 3
Output Drive Current, Sink IOL 1.3 mAdc VDD 10 Vdc; VOL = 0.5 Vdc; TA 25°C 3
Output Drive Current, Sink IOL 3.4 mAdc VDD 15 Vdc; VOL = 1.5 Vdc; TA 25°C 3
Input Current Iin 0.1 µAdc VDD 15 Vdc; TA −55°C 3
Input Current Iin 1 µAdc VDD 15 Vdc; TA 125°C 3
Input Capacitance Cin 7.5 pF Vin = 0 3
Quiescent Current (Per Package) IDD 0.25 µAdc VDD 5.0 Vdc; TA 25°C 3
Quiescent Current (Per Package) IDD 0.5 µAdc VDD 10 Vdc; TA 25°C 3
Quiescent Current (Per Package) IDD 1 µAdc VDD 15 Vdc; TA 25°C 3
Quiescent Current (Per Package) IDD 7.5 µAdc VDD 5.0 Vdc; TA 125°C 3
Quiescent Current (Per Package) IDD 15 µAdc VDD 10 Vdc; TA 125°C 3
Quiescent Current (Per Package) IDD 30 µAdc VDD 15 Vdc; TA 125°C 3
Hysteresis Voltage VH 0.3 Vdc VDD 5.0 Vdc; TA 25°C 3
Hysteresis Voltage VH 1.2 Vdc VDD 10 Vdc; TA 25°C 3
Hysteresis Voltage VH 1.6 Vdc VDD 15 Vdc; TA 25°C 3
Hysteresis Voltage VH 2 Vdc VDD 5.0 Vdc; TA 25°C 3
Hysteresis Voltage VH 3.4 Vdc VDD 10 Vdc; TA 25°C 3
Hysteresis Voltage VH 5 Vdc VDD 15 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 2.2 Vdc VDD 5.0 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 4.6 Vdc VDD 10 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 6.8 Vdc VDD 15 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 3.6 Vdc VDD 5.0 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 7.1 Vdc VDD 10 Vdc; TA 25°C 3
Threshold Voltage, Positive-Going VT+ 10.8 Vdc VDD 15 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 0.9 Vdc VDD 5.0 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 2.5 Vdc VDD 10 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 4 Vdc VDD 15 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 2.8 Vdc VDD 5.0 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 5.2 Vdc VDD 10 Vdc; TA 25°C 3
Threshold Voltage, Negative-Going VT- 7.4 Vdc VDD 15 Vdc; TA 25°C 3
Output Rise Time tTLH 200 ns CL = 50 pF, TA = 25°C; VDD 5.0 Vdc 4
Output Rise Time tTLH 100 ns CL = 50 pF, TA = 25°C; VDD 10 Vdc 4
Output Rise Time tTLH 80 ns CL = 50 pF, TA = 25°C; VDD 15 Vdc 4
Output Fall Time tTHL 200 ns CL = 50 pF, TA = 25°C; VDD 5.0 Vdc 4
Output Fall Time tTHL 100 ns CL = 50 pF, TA = 25°C; VDD 10 Vdc 4
Output Fall Time tTHL 80 ns CL = 50 pF, TA = 25°C; VDD 15 Vdc 4
Propagation Delay Time tPLH, tPHL 250 ns CL = 50 pF, TA = 25°C; VDD 5.0 Vdc 4
Propagation Delay Time tPLH, tPHL 100 ns CL = 50 pF, TA = 25°C; VDD 10 Vdc 4
Propagation Delay Time tPLH, tPHL 80 ns CL = 50 pF, TA = 25°C; VDD 15 Vdc 4
DC Supply Voltage Range VDD -0.5 18 V 1
Input or Output Voltage Range (DC or Transient); maximum is VDD + 0.5 V Vin, Vout -0.5 V DC or Transient 1
Input or Output Current (DC or Transient) per pin Iin, Iout 10 mA DC or Transient, per pin 1
Power Dissipation, per Package PD 500 mW per package (Note 1) 1
Ambient Temperature Range TA -55 125 °C 1
Storage Temperature Range Tstg -65 150 °C 1
Lead Temperature TL 260 °C 8-second soldering 1
Supply Voltage Range VDD 3 18 Vdc 1
Temperature Derating, Power Dissipation (D/DW packages) -7 mW/°C From 65°C to 125°C (Note 1) 1

CAD (KiCad official)

  • Symbol: HT4093ARZ
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: ht4093arz-etched.step / ht4093arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht4093arz.step / ht4093arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (7 pp, sha256 b7aa7407b6636c01, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF