component
HT4015ARZ
Public Made by Adomby adom
HTCSEMI Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ht4015arz",
"version": "0.1.0",
"type": "component",
"description": "HTCSEMI Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"logic",
"ht4015arz",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
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"path": "docs/hero.png"
},
"files": [
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"README.md",
"ht4015arz.kicad_sym",
"ht4015arz.kicad_mod",
"ht4015arz.glb",
"ht4015arz.step",
"ht4015arz.lbr",
"docs/hero.png",
"docs/ht4015arz-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ht4015arz-hero.glb",
"ht4015arz-hero.overlay.json",
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],
"component": {
"mpn": "HT4015ARZ",
"manufacturer": "HTCSEMI",
"package": "SOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shift Registers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234538875260928",
"parts": {
"symbol": "ht4015arz.kicad_sym",
"footprint": "ht4015arz.kicad_mod",
"model_3d": "ht4015arz-hero.glb",
"model_3d_plain": "ht4015arz-etched.glb",
"model_3d_step": "ht4015arz-etched.step",
"model_3d_step_plain": "ht4015arz.step",
"lbr": "ht4015arz.lbr"
},
"distributor_links": {
"lcsc": "C3019538"
},
"distributor_check": {
"checked_at": "2026-10-19T03:15:15Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "no match"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "CB",
"type": "input",
"description": "Clock input for register B; data shifts from stage to stage on the positive-going clock transition, and input levels must stay between VSS and VDD."
},
{
"number": "2",
"name": "Q3B",
"type": "output",
"description": "Stage 4 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "3",
"name": "Q2A",
"type": "output",
"description": "Stage 3 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "4",
"name": "Q1A",
"type": "output",
"description": "Stage 2 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "5",
"name": "Q0A",
"type": "output",
"description": "Stage 1 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "6",
"name": "RA",
"type": "input",
"description": "Reset input for register A; a high level clears all stages of register A to 0, and input levels must stay between VSS and VDD."
},
{
"number": "7",
"name": "DA",
"type": "input",
"description": "Serial data input for register A; input levels must stay between VSS and VDD, and diode protection is provided on all inputs."
},
{
"number": "8",
"name": "VSS",
"type": "power_in",
"description": "Ground reference for the device; all voltages in the datasheet are referenced to VSS."
},
{
"number": "9",
"name": "CA",
"type": "input",
"description": "Clock input for register A; data shifts from stage to stage on the positive-going clock transition, and input levels must stay between VSS and VDD."
},
{
"number": "10",
"name": "Q3A",
"type": "output",
"description": "Stage 4 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "11",
"name": "Q2B",
"type": "output",
"description": "Stage 3 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "12",
"name": "Q1B",
"type": "output",
"description": "Stage 2 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "13",
"name": "Q0B",
"type": "output",
"description": "Stage 1 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range."
},
{
"number": "14",
"name": "RB",
"type": "input",
"description": "Reset input for register B; a high level clears all stages of register B to 0, and input levels must stay between VSS and VDD."
},
{
"number": "15",
"name": "DB",
"type": "input",
"description": "Serial data input for register B; input levels must stay between VSS and VDD, and diode protection is provided on all inputs."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "Positive supply pin, rated 3.0 Vdc to 18 Vdc; the absolute maximum DC supply is -0.5 V to +18.0 V."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin assignment on page 2 is a scrambled text layout. Pin numbers were taken from the standard le; The package mapping comes from the page 1 marking, which lists HT4015ARZ under 'SOP-16 R SUFFIX'. Th; Descriptions for input pins reuse the datasheet's general statements about voltage limits and diode "
],
"pages_sent": 9,
"cost_usd": 0.05,
"at": "2026-10-19T03:12:46"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234538875260928",
"pages": 9,
"sha256": "3e1c40109932bb52",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ht4015arz.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.0,
9.9,
1.75
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-19",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ht4015arz-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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"sha256": "14e2cdc63262fc7863a9295955fee2ec6da8bfe91dbae3049d67054fb07c1425",
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}
]
}
}