# HT4015ARZ

**HTCSEMI** · Shift Registers · SOP-16

HT4015ARZ from HTCSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB | input | Clock input for register B; data shifts from stage to stage on the positive-going clock transition, and input levels must stay between VSS and VDD. |
| 2 | Q3B | output | Stage 4 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 3 | Q2A | output | Stage 3 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 4 | Q1A | output | Stage 2 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 5 | Q0A | output | Stage 1 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 6 | RA | input | Reset input for register A; a high level clears all stages of register A to 0, and input levels must stay between VSS and VDD. |
| 7 | DA | input | Serial data input for register A; input levels must stay between VSS and VDD, and diode protection is provided on all inputs. |
| 8 | VSS | power_in | Ground reference for the device; all voltages in the datasheet are referenced to VSS. |
| 9 | CA | input | Clock input for register A; data shifts from stage to stage on the positive-going clock transition, and input levels must stay between VSS and VDD. |
| 10 | Q3A | output | Stage 4 output of register A; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 11 | Q2B | output | Stage 3 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 12 | Q1B | output | Stage 2 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 13 | Q0B | output | Stage 1 output of register B; the output can drive two low-power TTL loads or one low-power Schottky TTL load over the rated temperature range. |
| 14 | RB | input | Reset input for register B; a high level clears all stages of register B to 0, and input levels must stay between VSS and VDD. |
| 15 | DB | input | Serial data input for register B; input levels must stay between VSS and VDD, and diode protection is provided on all inputs. |
| 16 | VDD | power_in | Positive supply pin, rated 3.0 Vdc to 18 Vdc; the absolute maximum DC supply is -0.5 V to +18.0 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC Supply Voltage Range (absolute maximum) | VDD | -0.5 |  | 18 | V | Voltages referenced to VSS | 1 |
| Input or Output Voltage Range (DC or Transient) | Vin, Vout | -0.5 |  |  | V | DC or transient; printed maximum is VDD + 0.5 V, no numeric value | 1 |
| Input or Output Current (DC or Transient) per pin | Iin, Iout |  |  | 10 | mA | DC or transient, per pin | 1 |
| Power Dissipation, per Package | PD |  |  | 500 | mW | Per package (Note 1) | 1 |
| Ambient Temperature Range | TA | -55 |  | 125 | °C |  | 1 |
| Storage Temperature Range | Tstg | -65 |  | 150 | °C |  | 1 |
| Lead Temperature | TL |  |  | 260 | °C | 8-second soldering | 1 |
| Supply Voltage Range | VDD | 3 |  | 18 | Vdc | Stated in Features list | 1 |
| Output Voltage '0' Level | VOL |  | 0 | 0.05 | Vdc | VDD = 5.0 Vdc; Vin = VDD or 0; TA = 25°C | 3 |
| Output Voltage '1' Level | VOH | 4.95 | 5 |  | Vdc | VDD = 5.0 Vdc; Vin = 0 or VDD; TA = 25°C | 3 |
| Output Voltage '1' Level | VOH | 9.95 | 10 |  | Vdc | VDD = 10 Vdc; Vin = 0 or VDD; TA = 25°C | 3 |
| Output Voltage '1' Level | VOH | 14.95 | 15 |  | Vdc | VDD = 15 Vdc; Vin = 0 or VDD; TA = 25°C | 3 |
| Input Voltage '0' Level | VIL |  | 2.25 | 1.5 | Vdc | VO = 4.5 or .05 Vdc; VDD = 5.0 Vdc; TA = 25°C | 3 |
| Input Voltage '0' Level | VIL |  | 4.5 | 3 | Vdc | VO = 9.0 or 1.0 Vdc; VDD = 10 Vdc; TA = 25°C | 3 |
| Input Voltage '0' Level | VIL |  | 6.75 | 4 | Vdc | VO = 13.5 or 1.5 Vdc; VDD = 15 Vdc; TA = 25°C | 3 |
| Input Voltage '1' Level | VIH | 3.5 | 2.75 |  | Vdc | VO = 0.5 or 4.5 Vdc; VDD = 5.0 Vdc; TA = 25°C | 3 |
| Input Voltage '1' Level | VIH | 7 | 5.5 |  | Vdc | VO = 1.0 or 9.0 Vdc; VDD = 10 Vdc; TA = 25°C | 3 |
| Input Voltage '1' Level | VIH | 11 | 8.25 |  | Vdc | VO = 1.5 or 13.5 Vdc; VDD = 15 Vdc; TA = 25°C | 3 |
| Output Drive Current, Source | IOH | -2.4 | -4.2 |  | mAdc | VOH = 2.5 Vdc; VDD = 5.0 Vdc; TA = 25°C | 3 |
| Output Drive Current, Source | IOH | -0.51 | -0.88 |  | mAdc | VOH = 4.6 Vdc; VDD = 5.0 Vdc; TA = 25°C | 3 |
| Output Drive Current, Source | IOH | -1.3 | -2.25 |  | mAdc | VOH = 9.5 Vdc; VDD = 10 Vdc; TA = 25°C | 3 |
| Output Drive Current, Source | IOH | -3.4 | -8.8 |  | mAdc | VOH = 13.5 Vdc; VDD = 15 Vdc; TA = 25°C | 3 |
| Output Drive Current, Sink | IOL | 0.51 | 0.88 |  | mAdc | VOL = 0.4 Vdc; VDD = 5.0 Vdc; TA = 25°C | 3 |
| Output Drive Current, Sink | IOL | 1.3 | 2.25 |  | mAdc | VOL = 0.5 Vdc; VDD = 10 Vdc; TA = 25°C | 3 |
| Output Drive Current, Sink | IOL | 3.4 | 8.8 |  | mAdc | VOL = 1.5 Vdc; VDD = 15 Vdc; TA = 25°C | 3 |
| Input Current | Iin |  | 1e-05 | 0.1 | mAdc | VDD = 15 Vdc; TA = 25°C | 3 |
| Input Capacitance | Cin |  | 5 | 7.5 | pF | Vin = 0; TA = 25°C | 3 |
| Quiescent Current (Per Package) | IDD |  | 0.005 | 5 | mAdc | VDD = 5.0 Vdc; TA = 25°C | 3 |
| Quiescent Current (Per Package) | IDD |  | 0.01 | 10 | mAdc | VDD = 10 Vdc; TA = 25°C | 3 |
| Quiescent Current (Per Package) | IDD |  | 0.015 | 20 | mAdc | VDD = 15 Vdc; TA = 25°C | 3 |
| Output Rise and Fall Time | tTLH, tTHL |  | 100 | 200 | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Output Rise and Fall Time | tTLH, tTHL |  | 50 | 100 | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Output Rise and Fall Time | tTLH, tTHL |  | 40 | 80 | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Clock, Data to Q | tPLH, tPHL |  | 310 | 750 | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Clock, Data to Q | tPLH, tPHL |  | 125 | 250 | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Clock, Data to Q | tPLH, tPHL |  | 90 | 170 | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Reset to Q | tPLH, tPHL |  | 460 | 750 | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Reset to Q | tPLH, tPHL |  | 180 | 250 | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Propagation Delay Time, Reset to Q | tPLH, tPHL |  | 120 | 170 | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Width | tWH | 400 | 185 |  | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Width | tWH | 175 | 85 |  | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Width | tWH | 135 | 55 |  | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Frequency | fcl |  | 2 | 1.5 | MHz | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Frequency | fcl |  | 6 | 3 | MHz | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Frequency | fcl |  | 7.5 | 3.75 | MHz | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Rise and Fall Times | tTLH, tTHL |  |  | 15 | ms | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Rise and Fall Times | tTLH, tTHL |  |  | 5 | ms | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Clock Pulse Rise and Fall Times | tTLH, tTHL |  |  | 4 | ms | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Reset Pulse Width | tWH | 400 | 200 |  | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Reset Pulse Width | tWH | 160 | 80 |  | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Reset Pulse Width | tWH | 120 | 60 |  | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |
| Setup Time | tsu | 350 | 100 |  | ns | VDD = 5.0 V; CL = 50 pF; TA = 25°C | 4 |
| Setup Time | tsu | 100 | 50 |  | ns | VDD = 10 V; CL = 50 pF; TA = 25°C | 4 |
| Setup Time | tsu | 75 | 40 |  | ns | VDD = 15 V; CL = 50 pF; TA = 25°C | 4 |

## CAD (KiCad official)

- Symbol: `HT4015ARZ`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `ht4015arz-etched.step` / `ht4015arz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ht4015arz.step` / `ht4015arz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HTCSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234538875260928) (9 pp, sha256 `3e1c40109932bb52`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ht4015arz-datasheet.pdf)