component
HT3605ARQZ
Public Made by Adomby adom
HTCSEMI DC-DC Converters, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownHT3605ARQZ
HTCSEMI · DC-DC Converters · QFN-24-EP(4x4)
HT3605ARQZ from HTCSEMI, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RT | passive | Switching frequency setting pin; a resistor from RT to GND adjusts the switching frequency from 800kHz to 2MHz. |
| 2 | PHMODE | input | Output phase selection pin setting the phase relationship between the internal oscillator and CLKOUT: connect to VCC for 2-phase, to SGND for 3-phase, to VCC/2 for 4-phase operation. |
| 3 | MODE | input | Mode selection pin: connect to VCC for forced continuous synchronous operation at all loads, to SGND for discontinuous mode at light load; do not float. |
| 4 | FB | input | Output voltage feedback pin; set the output voltage with a resistor divider between VOUT and GND. |
| 5 | TRACK/SS | input | Output tracking and soft-start pin; an external capacitor sets the output ramp time, below 0.6V it overrides the error amplifier internal reference, above 0.6V tracking stops and the internal reference resumes control. |
| 6 | ITH | output | Error amplifier output and switching regulator compensation point; the current comparator trip threshold is linearly proportional to this voltage, normal range 1.2V to 1.8V. |
| 7 | EN | input | Regulator output enable pin, high enables the output; an external resistor divider can set an adjustable VIN undervoltage lockout. |
| 8 | PG | output | Open-drain power-good indicator for the buck output voltage; the pull-down stops when the output is normal. |
| 9 | VON | input | Output voltage node; connect to the output voltage so on-time is proportional to VOUT and switching frequency stays constant across VOUT, but constant frequency is lost when VON is <0.6V or >6V. |
| 10 | PGND | power_in | Power ground pin; connect one or more decoupling ceramic capacitors to VIN as close to the pin as possible. |
| 11 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 12 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 13 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 14 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 15 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 16 | SW | power_out | Internal power switch node; connect the power inductor and the CBST capacitor externally. |
| 17 | PVIN | power_in | Regulator power supply input (4V to 20V); use a 2.2µF or larger ceramic capacitor placed as close as possible from VIN to GND. |
| 18 | PVIN | power_in | Regulator power supply input (4V to 20V); use a 2.2µF or larger ceramic capacitor placed as close as possible from VIN to GND. |
| 19 | SVIN | power_in | Regulator signal supply input; connect a 1Ω to 10Ω resistor between SVIN and PVIN and bypass to GND with a 0.1µF capacitor. |
| 20 | BST | passive | Bootstrap drive supply; requires a high-quality 100nF ceramic capacitor between BST and SW to bias the internal high-side gate driver. |
| 21 | VCC | power_out | Internal 3.3V regulator output; requires a 1µF to 4.7µF ceramic decoupling capacitor between VCC and PGND placed close to the pin. |
| 22 | SGND | power_in | Chip signal ground pin. |
| 23 | CLKOUT | output | Output clock signal for multiphase operation; its phase relative to CLKIN is set by the PHMODE pin and its amplitude is VCC to GND. |
| 24 | CLKIN | input | External clock synchronization input with an internal 20k termination to SGND; the phase-locked loop forces the top-power NMOS turn-on signal to sync with the CLKIN rising edge. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | QFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
HT3605ARQZ - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
ht3605arqz-etched.step/ht3605arqz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ht3605arqz.step/ht3605arqz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HTCSEMI datasheet (17 pp, sha256
a41232f8a27d2b61, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).