component
HT1381M
Public Made by Adomby adom
HGSEMI Real Time Clocks, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 10d ago |
| viewers | 10d ago |
| ht1381m-etched.glb | 10d ago |
| ht1381m-etched.step | 10d ago |
| ht1381m-hero.glb | 10d ago |
| ht1381m-hero.overlay.json | 10d ago |
| ht1381m.glb | 10d ago |
| ht1381m.kicad_mod | 10d ago |
| ht1381m.kicad_sym | 10d ago |
| ht1381m.lbr | 10d ago |
| ht1381m.step | 10d ago |
| package.json | 10d ago |
| page.json | 10d ago |
| README.md | 10d ago |
HT1381M
HGSEMI · Real Time Clocks · SOP-8
HT1381M from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | X1 | input | 32768Hz crystal input pad; a 9.0pF load-capacitance crystal is recommended and no additional load capacitors should be connected to X1 or X2. |
| 3 | X2 | output | Oscillator output pad for the 32768Hz crystal; no additional load capacitors should be connected to this pin. |
| 4 | VSS | power_in | Negative power supply and ground reference. |
| 5 | REST | input | Reset pin for serial transmission: taken high to enable access to the shift register, and taken low to terminate the transfer and place I/O in high impedance. |
| 6 | I/O | bidirectional | Serial data input/output; data is read after the SCLK rising edge and becomes output after the SCLK falling edge, going high impedance when REST is low. |
| 7 | SCLK | input | Serial clock input used to synchronize register reads and writes, with data entered on the rising edge and output on the falling edge. |
| 8 | VDD | power_in | Positive power supply, operating range 2.0V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-8 |
| Category | Clock/Timing |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | VDD | 0.3 | 5.5 | V | 3 | ||
| Operating Temperature (absolute maximum) | 0 | 70 | °C | 3 | |||
| VDD Operating Voltage | VDD | 2 | 5.5 | V | 4 | ||
| Standby Current | ISTB | 100 | nA | VDD=2V; SCLK, I/O, RST open; clock halt bit CH=1 | 4 | ||
| Operating Current | IDD | 0.7 | 1 | μA | VDD=2V, no load | 4 | |
| Operating Current | IDD | 0.7 | 1.2 | μA | VDD=5V, no load | 4 | |
| Source Current | IOH | 0.2 | 0.4 | mA | VDD=2V, VOH=1.8V | 4 | |
| Source Current | IOH | 0.5 | 1 | mA | VDD=5V, VOH=4.5V | 4 | |
| Sink Current | IOL | 0.7 | 1.5 | mA | VDD=2V, VOL=0.2V | 4 | |
| Sink Current | IOL | 2 | 4 | mA | VDD=5V, VOL=0.5V | 4 | |
| "H" Input Voltage | VIH | 2 | V | VDD=5V | 4 | ||
| "L" Input Voltage | VIL | 0.8 | V | VDD=5V | 4 | ||
| Data to Clock Setup | tDC | 200 | ns | VDD=2V | 5 | ||
| Data to Clock Setup | tDC | 50 | ns | VDD=5V | 5 | ||
| Clock to Data Hold | tCDH | 280 | ns | VDD=2V | 5 | ||
| Clock to Data Hold | tCDH | 70 | ns | VDD=5V | 5 | ||
| Clock to Data Delay | tCDD | 800 | ns | VDD=2V | 5 | ||
| Clock to Data Delay | tCDD | 200 | ns | VDD=5V | 5 | ||
| Clock Low Time | tCL | 1000 | ns | VDD=2V | 5 | ||
| Clock Low Time | tCL | 250 | ns | VDD=5V | 5 | ||
| Clock High Time | tCH | 1000 | ns | VDD=2V | 5 | ||
| Clock High Time | tCH | 250 | ns | VDD=5V | 5 | ||
| Clock Frequency | fSCLK | 0.5 | MHz | VDD=2V | 5 | ||
| Clock Frequency | fSCLK | 2 | MHz | VDD=5V | 5 | ||
| Clock Rise and Fall Time | tr, tf | 2000 | ns | VDD=2V | 5 | ||
| Clock Rise and Fall Time | tr, tf | 500 | ns | VDD=5V | 5 | ||
| Reset to Clock Setup | tCC | 4 | us | VDD=2V | 5 | ||
| Reset to Clock Setup | tCC | 1 | us | VDD=5V | 5 | ||
| Clock to Reset Hold | tCCH | 240 | ns | VDD=2V | 5 | ||
| Clock to Reset Hold | tCCH | 60 | ns | VDD=5V | 5 | ||
| Reset Inactive Time | tCWH | 4 | us | VDD=2V | 5 | ||
| Reset Inactive Time | tCWH | 1 | us | VDD=5V | 5 | ||
| Reset to I/O High Impedance | tCDZ | 280 | ns | VDD=2V | 5 | ||
| Reset to I/O High Impedance | tCDZ | 70 | ns | VDD=5V | 5 |
CAD (KiCad official)
- Symbol:
HT1381M - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ht1381m-etched.step/ht1381m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ht1381m.step/ht1381m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (16 pp, sha256
45d4dc6ac537feab, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).