component
HT1232ARZ
Public Made by Adomby adom
HTCSEMI Supervisor And Reset ICs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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HT1232ARZ
HTCSEMI · Supervisor And Reset ICs · SO-8
HT1232ARZ from HTCSEMI, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PBRST | input | Debounced active-low pushbutton reset input that ignores pulses shorter than 1ms and is guaranteed to recognize inputs of 20ms or greater, with an internal pull-up to VCC so no external pull-up is needed. |
| 2 | TD | input | Time-delay (watchdog timebase) select input: tTD = 150ms with TD at 0V, 600ms with TD open, and 1.2s with TD at VCC. |
| 3 | TOL | input | Tolerance select input: connect to GND for 5% supply tolerance (VCC trip point 4.50V to 4.74V) or to VCC for 10% tolerance (4.25V to 4.49V). |
| 4 | GND | power_in | Ground reference; all voltages are referenced to GND. |
| 5 | RST | output | Active-high reset output that goes active when VCC falls below the selected reset threshold, when PBRST is forced low, when ST is not strobed within the minimum timeout period, and during power-up. |
| 6 | RST | output | Active-low reset output implemented as an open-drain MOSFET that sinks current only and must be pulled high externally. |
| 7 | ST | input | Watchdog strobe input that must toggle (falling edges only, minimum pulse width 75ns) within the selected timeout period to prevent a watchdog reset. |
| 8 | VCC | power_in | +5V power supply input; the recommended DC operating range is 4.5V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage Range on Any Pin (with respect to GND) | -1 | 7 | V | with respect to GND | 2 | ||
| Operating Temperature Range | 0 | 70 | °C | C Suffix | 2 | ||
| Storage Temperature Range | -65 | 160 | °C | 2 | |||
| Lead Temperature | 300 | °C | soldering, 10s | 2 | |||
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | TA = TMIN to TMAX, unless otherwise noted | 2 |
| ST and PBRST Input High Level | VIH | 2 | V | Note 1; max printed as VCC + 0.3 | 2 | ||
| ST and PBRST Input Low Level | VIL | -0.3 | 0.8 | V | 2 | ||
| Input Leakage ST, TOL | IIL | -1 | 1 | µA | VCC = +4.5V to +5.5V, TA = TMIN to TMAX | 2 | |
| Output Current RST | IOH | -1 | -12 | mA | VOH = 2.4V | 2 | |
| Output Current RST, RST | IOL | 2 | 10 | mA | VOL = 0.4V | 2 | |
| Operating Current | ICC | 50 | 200 | µA | Note 2: measured with outputs open | 2 | |
| VCC 5% Trip Point | VCCTP | 4.5 | 4.62 | 4.74 | V | TOL = GND; Note 3 | 2 |
| VCC 10% Trip Point | VCCTP | 4.25 | 4.37 | 4.49 | V | TOL = VCC; Note 3 | 2 |
| PBRST | tPB | 20 | ms | Figure 3; Note 5 | 3 | ||
| PBRST Delay | tPBD | 1 | 4 | 20 | ms | Figure 3 | 3 |
| Reset Active Time | tRST | 250 | 610 | 1000 | ms | 3 | |
| ST Pulse Width | tST | 75 | ns | Figure 4 | 3 | ||
| ST Timeout Period | tTD | 62.5 | 150 | 250 | ms | Figure 4, TD pin = 0V | 3 |
| ST Timeout Period | tTD | 250 | 600 | 1000 | ms | Figure 4, TD pin = open | 3 |
| ST Timeout Period | tTD | 500 | 1200 | 2000 | ms | Figure 4, TD pin = VCC | 3 |
| VCC Fall Time | tF | 10 | µs | Figure 5; Note 4: guaranteed by design | 3 | ||
| VCC Rise Time | tB | 0 | µs | Figure 6; Note 4: guaranteed by design | 3 | ||
| VCC Detect to RST High and RST Low | tBPD | 100 | ns | Figure 7, VCC falling | 3 | ||
| VCC Detect to RST Low and RST Open | tBPU | 250 | 610 | 1000 | ms | Figure 8, VCC rising; Note 6: tR = 5µs | 3 |
| Input Capacitance ST, TOL | CIN | 5 | pF | TA = +25°C; Note 4 | 2 | ||
| Output Capacitance RST, RST | COUT | 7 | pF | TA = +25°C; Note 4 | 2 |
CAD (KiCad official)
- Symbol:
HT1232ARZ - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
ht1232arz-etched.step/ht1232arz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ht1232arz.step/ht1232arz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HTCSEMI datasheet (8 pp, sha256
039de738dd77f743, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# HT1232ARZ
**HTCSEMI** · Supervisor And Reset ICs · SO-8
HT1232ARZ from HTCSEMI, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PBRST | input | Debounced active-low pushbutton reset input that ignores pulses shorter than 1ms and is guaranteed to recognize inputs of 20ms or greater, with an internal pull-up to VCC so no external pull-up is needed. |
| 2 | TD | input | Time-delay (watchdog timebase) select input: tTD = 150ms with TD at 0V, 600ms with TD open, and 1.2s with TD at VCC. |
| 3 | TOL | input | Tolerance select input: connect to GND for 5% supply tolerance (VCC trip point 4.50V to 4.74V) or to VCC for 10% tolerance (4.25V to 4.49V). |
| 4 | GND | power_in | Ground reference; all voltages are referenced to GND. |
| 5 | RST | output | Active-high reset output that goes active when VCC falls below the selected reset threshold, when PBRST is forced low, when ST is not strobed within the minimum timeout period, and during power-up. |
| 6 | RST | output | Active-low reset output implemented as an open-drain MOSFET that sinks current only and must be pulled high externally. |
| 7 | ST | input | Watchdog strobe input that must toggle (falling edges only, minimum pulse width 75ns) within the selected timeout period to prevent a watchdog reset. |
| 8 | VCC | power_in | +5V power supply input; the recommended DC operating range is 4.5V to 5.5V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HTCSEMI |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage Range on Any Pin (with respect to GND) | | -1 | | 7 | V | with respect to GND | 2 |
| Operating Temperature Range | | 0 | | 70 | °C | C Suffix | 2 |
| Storage Temperature Range | | -65 | | 160 | °C | | 2 |
| Lead Temperature | | | | 300 | °C | soldering, 10s | 2 |
| Supply Voltage | VCC | 4.5 | 5 | 5.5 | V | TA = TMIN to TMAX, unless otherwise noted | 2 |
| ST and PBRST Input High Level | VIH | 2 | | | V | Note 1; max printed as VCC + 0.3 | 2 |
| ST and PBRST Input Low Level | VIL | -0.3 | | 0.8 | V | | 2 |
| Input Leakage ST, TOL | IIL | -1 | | 1 | µA | VCC = +4.5V to +5.5V, TA = TMIN to TMAX | 2 |
| Output Current RST | IOH | -1 | | -12 | mA | VOH = 2.4V | 2 |
| Output Current RST, RST | IOL | 2 | | 10 | mA | VOL = 0.4V | 2 |
| Operating Current | ICC | | 50 | 200 | µA | Note 2: measured with outputs open | 2 |
| VCC 5% Trip Point | VCCTP | 4.5 | 4.62 | 4.74 | V | TOL = GND; Note 3 | 2 |
| VCC 10% Trip Point | VCCTP | 4.25 | 4.37 | 4.49 | V | TOL = VCC; Note 3 | 2 |
| PBRST | tPB | 20 | | | ms | Figure 3; Note 5 | 3 |
| PBRST Delay | tPBD | 1 | 4 | 20 | ms | Figure 3 | 3 |
| Reset Active Time | tRST | 250 | 610 | 1000 | ms | | 3 |
| ST Pulse Width | tST | 75 | | | ns | Figure 4 | 3 |
| ST Timeout Period | tTD | 62.5 | 150 | 250 | ms | Figure 4, TD pin = 0V | 3 |
| ST Timeout Period | tTD | 250 | 600 | 1000 | ms | Figure 4, TD pin = open | 3 |
| ST Timeout Period | tTD | 500 | 1200 | 2000 | ms | Figure 4, TD pin = VCC | 3 |
| VCC Fall Time | tF | 10 | | | µs | Figure 5; Note 4: guaranteed by design | 3 |
| VCC Rise Time | tB | 0 | | | µs | Figure 6; Note 4: guaranteed by design | 3 |
| VCC Detect to RST High and RST Low | tBPD | | | 100 | ns | Figure 7, VCC falling | 3 |
| VCC Detect to RST Low and RST Open | tBPU | 250 | 610 | 1000 | ms | Figure 8, VCC rising; Note 6: tR = 5µs | 3 |
| Input Capacitance ST, TOL | CIN | | 5 | | pF | TA = +25°C; Note 4 | 2 |
| Output Capacitance RST, RST | COUT | | 7 | | pF | TA = +25°C; Note 4 | 2 |
## CAD (KiCad official)
- Symbol: `HT1232ARZ`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `ht1232arz-etched.step` / `ht1232arz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ht1232arz.step` / `ht1232arz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HTCSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588945471758323712) (8 pp, sha256 `039de738dd77f743`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ht1232arz-datasheet.pdf)