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HT1062BNZ

HTCSEMI · Analog To Digital Converters (ADCs) · DIP-16

HT1062BNZ from HTCSEMI, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LN	power_in	Positive line terminal; the regulated line voltage VLN is typically 4.0 V at Iline = 15 mA, with absolute maximum continuous line voltage 12 V.
2	GAS1	passive	Transmitting amplifier gain adjustment; R7 between GAS1 and GAS2 sets microphone gain between 44 dB and 52 dB, with C6 to SLPE and C8 to VEE for stability.
3	GAS2	passive	Transmitting amplifier gain adjustment; R7 (68 k for typically 52 dB) is connected between GAS1 and GAS2.
4	QR	output	Non-inverting output of the receiving amplifier, with output impedance of about 4 ohms; R4 between GAR and QR sets the gain.
5	GAR	passive	Receiving amplifier gain adjustment; R4 between GAR and QR sets IR-to-QR gain between 20 dB and 31 dB (31 dB typical with R4 = 100 k).
6	MIC-	input	Inverting microphone input with 64 k differential input impedance (32 k single-ended to VEE) for dynamic, magnetic, piezo-electric or electret microphones.
7	MIC+	input	Non-inverting microphone input with 64 k differential input impedance (32 k single-ended to VEE), typical gain 52 dB to LN with R7 = 68 k.
8	STAB	passive	Current stabilizer pin; a 3.6 k resistor from STAB to VEE sets the stabilizer current level.
9	VEE	power_in	Negative line terminal (ground reference, VEE = 0 V).
10	IR	input	Receiving amplifier input with about 21 k input impedance.
11	DTMF	input	Dual-tone multi-frequency input with about 20.7 k input impedance and typical gain to LN of 25.5 dB (R7 = 68 k), with confidence tone in the earpiece.
12	MUTE	input	Mute input, active HIGH on the HT1062B (HIGH level input at least 1.5 V up to VCC, LOW level at most 0.3 V), selecting DTMF versus microphone and receiving amplifier.
13	VCC	power_out	Positive supply decoupling pin that also supplies external circuits, with typical VCC of 2.2 V minimum at Iline = 15 mA and Ip = 1.2 mA (2.7 V typical at Ip = 0 mA) and internal supply current of 0.9 to 1.35 mA at VCC = 2.8 V.
14	REG	passive	Voltage regulator decoupling pin with a capacitor to VEE; RVA from REG to SLPE raises, and from LN to REG lowers, the DC line voltage.
15	AGC	input	Automatic gain control input; R6 to VEE sets line-loss compensation with a 5.8 dB control range, and the pin may be left open for no compensation.
16	SLPE	passive	Slope (DC resistance) adjustment pin; external resistor R9 (normally 20 ohms) between SLPE and VEE sets the DC slope of the line voltage.

Key specifications

Parameter	Value
Manufacturer	HTCSEMI
Package	DIP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Positive continuous line voltage	VLN			12	V		11
Repetitive line voltage during switch-on or line interruption	VLN(R)			13.2	V		11
Repetitive peak line voltage for a 1ms pulse per 5s	VLN(RM)			28	V	R9 = 20; R10 = 13; see Fig.6	11
Line current	Iline			140	mA	R9 = 20; note 1	11
Input voltage on all other pins	VI	-0.7		0.7	V	max printed as VCC+0.7	11
Total power dissipation, standard DIP	Ptot			0.58	W	R9 = 20; note 2	11
Operating ambient temperature	TA	-25		75	°C		11
Storage temperature	Tstg	-40		125	°C		11
Junction temperature	Tj			125	°C		11
Thermal resistance, standard DIP	RthJA		85		°C/W	standard DIP	11
Voltage drop over circuit LN to VEE	VLN	3.55	4	4.25	V	MIC inputs open-circuit; Iline = 15mA	12
Supply current	ICC		0.9	1.35	mA	VCC = 2.8V	12
Supply voltage for peripheral circuitry	VCC		2.2		V	Iline = 15mA; Ip = 1.2mA	12
Voltage gain MIC+ or MIC- to LN	Gv	50.5	52	53.5	dB	Iline = 15mA; R7 = 68k	12
Voltage gain IR to QR	Gv	29.5	31	32.5	dB	Iline = 15mA; RL = 300; (from pin 9 to pin 4)	13
MUTE HIGH level input voltage	VIH	1.5			V	Iline = 15 mA	13
Highest line current for maximum gain	IlineH	20		23	mA	Iline = 15 mA	13
Lowest line current for minimum gain	IlineL	61		65	mA	Iline = 70 mA	13
Receiving amplifier gain variation by R4	Gv	-11		0	dB	Iline = 15mA; RL = 300; (from pin 9 to pin 4)	13
Transmitting amplifier gain variation by R7	Gv	-8		0	dB		12
Variation of VLN with temperature	ΔVLN/ΔT		-0.3		mV/°C	Iline = 15mA	12

CAD (KiCad official)

Symbol: HT1062BNZ
Footprint: Package_DIP:DIP-16_W7.62mm
3D model: DIP-16 (KiCad packages3D, STEP)
3D model files: ht1062bnz-etched.step / ht1062bnz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht1062bnz.step / ht1062bnz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: HTCSEMI datasheet (16 pp, sha256 7b77ca8d7beca36c, retrieved 2026-10-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF