# HMCAD1511TR

**Analog Devices** · Analog To Digital Converters (ADC) · QFN-48-EP(7x7)

HMCAD1511TR from Analog Devices, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | Analog power supply, 1.8V; pin 36 is also AVDD. |
| 2 | CSN | input | Chip select enable for the serial interface, active low; serial data is shifted in while CSN is low. |
| 3 | SDATA | input | Serial interface data input, latched at every rising edge of SCLK. |
| 4 | SCLK | input | Serial interface clock input; acceptable frequencies run from 20 MHz down to a few hertz and duty cycle need not be tightly controlled. |
| 5 | RESETN | input | Active-low reset of the SPI interface; a low-going pulse of minimum 20 ns resets the device asynchronously. |
| 6 | PD | input | Power-down input to be activated after power is applied to initialize the ADC correctly; a high-going pulse of minimum 20 ns powers down asynchronously, or the SPI pd feature can be used instead. |
| 7 | DVDD | power_in | Digital and I/O power supply, 1.8V; pin 30 is also DVDD. |
| 8 | DVSS | power_in | Digital ground; pin 29 is also DVSS. |
| 9 | DP1A | output | LVDS channel 1A positive output, forming a differential pair with DN1A. |
| 10 | DN1A | output | LVDS channel 1A negative output, forming a differential pair with DP1A. |
| 11 | DP1B | output | LVDS channel 1B positive output, forming a differential pair with DN1B. |
| 12 | DN1B | output | LVDS channel 1B negative output, forming a differential pair with DP1B. |
| 13 | DP2A | output | LVDS channel 2A positive output, forming a differential pair with DN2A. |
| 14 | DN2A | output | LVDS channel 2A negative output, forming a differential pair with DP2A. |
| 15 | DP2B | output | LVDS channel 2B positive output, forming a differential pair with DN2B. |
| 16 | DN2B | output | LVDS channel 2B negative output, forming a differential pair with DP2B. |
| 17 | LCLKP | output | LVDS bit clock positive output, forming a differential pair with LCLKN. |
| 18 | LCLKN | output | LVDS bit clock negative output, forming a differential pair with LCLKP. |
| 19 | FCLKP | output | LVDS frame clock (1X) positive output, forming a differential pair with FCLKN. |
| 20 | FCLKN | output | LVDS frame clock (1X) negative output, forming a differential pair with FCLKP. |
| 21 | DP3A | output | LVDS channel 3A positive output, forming a differential pair with DN3A. |
| 22 | DN3A | output | LVDS channel 3A negative output, forming a differential pair with DP3A. |
| 23 | DP3B | output | LVDS channel 3B positive output, forming a differential pair with DN3B. |
| 24 | DN3B | output | LVDS channel 3B negative output, forming a differential pair with DP3B. |
| 25 | DP4A | output | LVDS channel 4A positive output, forming a differential pair with DN4A. |
| 26 | DN4A | output | LVDS channel 4A negative output, forming a differential pair with DP4A. |
| 27 | DP4B | output | LVDS channel 4B positive output, forming a differential pair with DN4B. |
| 28 | DN4B | output | LVDS channel 4B negative output, forming a differential pair with DP4B. |
| 29 | DVSS | power_in | Digital ground; pin 8 is also DVSS. |
| 30 | DVDD | power_in | Digital and I/O power supply, 1.8V; pin 7 is also DVDD. |
| 31 | AVSS2 | power_in | Analog ground domain 2. |
| 32 | AVDD2 | power_in | Analog power supply domain 2, 1.8V. |
| 33 | OVDD | power_in | Digital CMOS inputs supply voltage. |
| 34 | CLKN | input | Negative differential input clock. |
| 35 | CLKP | input | Positive differential input clock. |
| 36 | AVDD | power_in | Analog power supply, 1.8V; pin 1 is also AVDD. |
| 37 | IN4 | input | Negative differential analog input signal, channel 4. |
| 38 | IP4 | input | Positive differential analog input signal, channel 4. |
| 39 | AVSS | power_in | Analog ground; pins 42 and 45 are also AVSS. |
| 40 | IN3 | input | Negative differential analog input signal, channel 3. |
| 41 | IP3 | input | Positive differential analog input signal, channel 3. |
| 42 | AVSS | power_in | Analog ground; pins 39 and 45 are also AVSS. |
| 43 | IN2 | input | Negative differential analog input signal, channel 2. |
| 44 | IP2 | input | Positive differential analog input signal, channel 2. |
| 45 | AVSS | power_in | Analog ground; pins 39 and 42 are also AVSS. |
| 46 | IN1 | input | Negative differential analog input signal, channel 1. |
| 47 | IP1 | input | Positive differential analog input signal, channel 1. |
| 48 | VCM | output | Common mode output pin at 0.5*AVDD. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-48-EP(7x7) |
| Category | Data Acquisition |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Clock input DC duty cycle |  | 45 |  | 55 | % high |  | 4 |
| LVDS bit-clock duty cycle |  | 45 |  | 55 | % LCLK cycle |  | 5 |
| Low level input voltage (CMOS logic inputs) | VLI | 0 |  | 0.8 | V | VOVDD ≥ 3.0V | 4 |
| High level input leakage current | IHI | -10 |  | 10 | µA |  | 4 |
| Low level input leakage current | ILI | -10 |  | 10 | µA |  | 4 |
| AVDD voltage (reference AVSS) | AVDD | -0.3 |  | 2.3 | V | Reference pin AVSS | 5 |
| DVDD voltage (reference DVSS) | DVDD | -0.3 |  | 2.3 | V | Reference pin DVSS | 5 |
| OVDD voltage (reference AVSS) | OVDD | -0.3 |  | 3.9 | V | Reference pin AVSS | 5 |
| AVSS / DVSS voltage | AVSS/DVSS | -0.3 |  | 0.3 | V | Reference pin DVSS / AVSS | 5 |
| Analog inputs and outputs voltage (reference AVSS) |  | -0.3 |  | 2.3 | V | Reference pin AVSS | 5 |
| CLKx voltage (reference AVSS) | CLKx | -0.3 |  | 3.9 | V | Reference pin AVSS | 5 |
| LVDS outputs voltage (reference DVSS) |  | -0.3 |  | 2.3 | V | Reference pin DVSS | 5 |
| Digital inputs voltage (reference DVSS) |  | -0.3 |  | 3.9 | V | Reference pin DVSS | 5 |
| Operating temperature |  | -40 |  | 85 | °C |  | 5 |
| Storage temperature |  | -60 |  | 150 | °C |  | 5 |
| Maximum junction temperature |  |  |  | 110 | °C |  | 5 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Part Number Package Body Material Lead Finish MSL [1] Package Marking [2] HMCAD1511 RoHS-compliant Low Stress Injection Molded Plastic 100% matte Sn Level 2A HAD1511 | 30 |

## CAD (KiCad official)

- Symbol: `HMCAD1511TR`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files: `hmcad1511tr-etched.step` / `hmcad1511tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hmcad1511tr.step` / `hmcad1511tr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893290901356544) (30 pp, sha256 `a28daf06a213ac7d`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hmcad1511tr-datasheet.pdf)