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HMC7043LP7FETR

Public Made by Adom

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Analog Devices Clock Generators, PLLs, Frequency Synthesizers, LFCSP-48(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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HMC7043LP7FETR

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-48(7x7)

HMC7043LP7FETR from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKOUT0 output True Clock Output Channel 0 with default DCLK profile.
2 CLKOUT0 output Complementary Clock Output Channel 0 with default DCLK profile.
3 SCLKOUT1 output True Clock Output Channel 1 with default SYSREF profile.
4 SCLKOUT1 output Complementary Clock Output Channel 1 with default SYSREF profile.
5 RESET input Device Reset Input, active high; set to Logic 0 for normal operation.
6 BGAPBYP1 passive Band Gap Bypass Capacitor Connection; connect 4.7 µF capacitor to ground, affects all internally regulated supplies.
7 LDOBYP2 passive LDO Bypass 2 for internal 1.8 V digital supply; connect 4.7 µF capacitor to ground.
8 VCC1_CLKDIST power_in 3.3 V Power Supply for CLK Distribution path.
9 SCLKOUT3 output True Clock Output Channel 3 with default SYSREF profile.
10 SCLKOUT3 output Complementary Clock Output Channel 3 with default SYSREF profile.
11 CLKOUT2 output True Clock Output Channel 2 with default DCLK profile.
12 CLKOUT2 output Complementary Clock Output Channel 2 with default DCLK profile.
13 VCC2_OUT power_in 3.3 V Power Supply for Clock Group 1 (Southwest), serving Channels 2 and 3.
14 RSV passive Reserved Pin; must be tied to ground.
15 SCLKOUT5 output True Clock Output Channel 5 with default SYSREF profile.
16 SCLKOUT5 output Complementary Clock Output Channel 5 with default SYSREF profile.
17 CLKOUT4 output True Clock Output Channel 4 with default DCLK profile.
18 CLKOUT4 output Complementary Clock Output Channel 4 with default DCLK profile.
19 VCC3_OUT power_in 3.3 V Power Supply for Clock Group 2 (South), serving Channels 4, 5, 6, and 7.
20 CLKOUT6 output True Clock Output Channel 6 with default DCLK profile.
21 CLKOUT6 output Complementary Clock Output Channel 6 with default DCLK profile.
22 SCLKOUT7 output True Clock Output Channel 7 with default SYSREF profile.
23 SCLKOUT7 output Complementary Clock Output Channel 7 with default SYSREF profile.
24 RSV passive Reserved Pin; must be tied to ground.
25 CLKIN input Complementary Clock Input.
26 CLKIN input True Clock Input.
27 VCC4_CLKIN power_in 3.3 V Power Supply for Clock Input Path.
28 RFSYNCIN input True RF Synchronization Input with Deterministic Delay.
29 RFSYNCIN input Complementary RF Synchronization Input with Deterministic Delay.
30 VCC5_SYSREF power_in 3.3 V Power Supply for Common SYSREF Divider.
31 SLEN bidirectional SPI Latch Enable; bidirectional signal for SPI serial communication.
32 SCLK bidirectional SPI Clock; bidirectional signal for SPI serial communication.
33 SDATA bidirectional SPI Data; bidirectional signal for SPI serial communication.
34 GPIO bidirectional Programmable General-Purpose Input/Output; configurable as input or output.
35 SCLKOUT9 output True Clock Output Channel 9 with default SYSREF profile.
36 SCLKOUT9 output Complementary Clock Output Channel 9 with default SYSREF profile.
37 CLKOUT8 output True Clock Output Channel 8 with default DCLK profile.
38 CLKOUT8 output Complementary Clock Output Channel 8 with default DCLK profile.
39 VCC6_OUT power_in 3.3 V Power Supply for Clock Group 3 (North), serving Channels 8, 9, 10, and 11.
40 CLKOUT10 output True Clock Output Channel 10 with default DCLK profile.
41 CLKOUT10 output Complementary Clock Output Channel 10 with default DCLK profile.
42 SCLKOUT11 output True Clock Output Channel 11 with default SYSREF profile.
43 SCLKOUT11 output Complementary Clock Output Channel 11 with default SYSREF profile.
44 SCLKOUT13 output True Clock Output Channel 13 with default SYSREF profile.
45 SCLKOUT13 output Complementary Clock Output Channel 13 with default SYSREF profile.
46 CLKOUT12 output True Clock Output Channel 12 with default DCLK profile.
47 CLKOUT12 output Complementary Clock Output Channel 12 with default DCLK profile.
48 VCC7_OUT power_in 3.3 V Power Supply for Clock Group 0 (Northwest), serving Channels 0, 1, 12, and 13.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: HMC7043LP7FETR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: hmc7043lp7fetr-etched.step / hmc7043lp7fetr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hmc7043lp7fetr.step / hmc7043lp7fetr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (43 pp, sha256 cda7ebf53ba358f0, retrieved 2026-09-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF