component
HIP4082IPZ
Public Made by Adomby adom
RENESAS Pre-ordered Chips, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHIP4082IPZ
RENESAS · Pre-ordered Chips · PDIP-16
HIP4082IPZ from RENESAS, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BHB | power_in | B High-side bootstrap supply; connect cathode of external bootstrap diode and positive side of bootstrap capacitor here (operating range VBHS+7.5V to VBHS+VDD). |
| 2 | BHI | input | B High-side logic input controlling BHO; BLI high overrides it to prevent shoot-through, DIS high overrides it, and it accepts 0V to 15V (no greater than VDD). |
| 3 | BLI | input | B Low-side logic input controlling BLO; if BHI is high or unconnected BLI controls both BLO and BHO with dead time set at DEL, DIS high overrides it, and it accepts 0V to 15V (no greater than VDD). |
| 4 | ALI | input | A Low-side logic input controlling ALO; if AHI is high or unconnected ALI controls both ALO and AHO with dead time set at DEL, DIS high overrides it, and it accepts 0V to 15V (no greater than VDD). |
| 5 | DEL | passive | Turn-on delay pin: connect a resistor to VSS to set the dead time between drivers (0.1 to 4.5us), with about VDD-2V across the resistor and input current limited to -4mA to -100uA. |
| 6 | VSS | power_in | Chip negative supply, generally ground; operating voltage -1.0V to +1.0V. |
| 7 | AHI | input | A High-side logic input controlling AHO; ALI high overrides it to prevent shoot-through, DIS high overrides it, and it accepts 0V to 15V (no greater than VDD). |
| 8 | DIS | input | Disable input: when taken high sets all four outputs low and overrides all other inputs, and it accepts 0V to 15V (no greater than VDD). |
| 9 | AHB | power_in | A High-side bootstrap supply; connect cathode of external bootstrap diode and positive side of bootstrap capacitor here (operating range VAHS+7.5V to VAHS+VDD). |
| 10 | AHO | output | A High-side output; connect to gate of A High-side power MOSFET. |
| 11 | AHS | passive | A High-side source connection to source of A High-side power MOSFET and negative side of bootstrap capacitor; rated -6V (transient) to 80V (25°C to 150°C). |
| 12 | VDD | power_in | Positive supply to control logic and lower gate drivers, operating range +8.5V to +15V; decouple to VSS (pin 6). |
| 13 | ALO | output | A Low-side output; connect to gate of A Low-side power MOSFET. |
| 14 | BLO | output | B Low-side output; connect to gate of B Low-side power MOSFET. |
| 15 | BHS | passive | B High-side source connection to source of B High-side power MOSFET and negative side of bootstrap capacitor; rated -6V (transient) to 80V (25°C to 150°C). |
| 16 | BHO | output | B High-side output; connect to gate of B High-side power MOSFET. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | PDIP-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (abs max) | VDD | -0.3 | 16 | V | relative to VSS | 5 | |
| Voltage on AHS, BHS (25C to 150C) | VAHS, VBHS | -6 | 80 | V | -6V (Transient) to 80V (25°C to 150°C) | 5 | |
| Voltage on AHS, BHS (-55C to 150C) | VAHS, VBHS | -6 | 70 | V | -6V (Transient) to 70V (-55°C to 150°C) | 5 | |
| Input Current, DEL (abs max) | -5 | 0 | mA | 5 | |||
| Phase Slew Rate | 20 | V/ns | 5 | ||||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Operating Max. Junction Temperature | TJ | 150 | °C | 5 | |||
| Lead Temperature (Soldering 10s) | 300 | °C | For SOIC - Lead Tips Only | 5 | |||
| Thermal Resistance, DIP Package | θJA | 90 | °C/W | DIP Package | 5 | ||
| Supply Voltage (operating) | VDD | 8.5 | 15 | V | 5 | ||
| Voltage on VSS | VSS | -1 | 1 | V | 5 | ||
| VDD Quiescent Current | IDD | 1.2 | 2.3 | 3.5 | mA | All inputs = 0V, RDEL = 100K, TJ=+25°C | 5 |
| VDD Quiescent Current (full range) | IDD | 0.85 | 4 | mA | All inputs = 0V, RDEL = 100K, TJ=-55°C to +150°C | 5 | |
| VDD Quiescent Current | IDD | 2.2 | 4 | 5.5 | mA | All inputs = 0V, RDEL = 10K, TJ=+25°C | 5 |
| VDD Operating Current | IDDO | 1.5 | 2.6 | 4 | mA | f = 50kHz, no load, TJ=+25°C | 5 |
| VDD Operating Current | IDDO | 2.5 | 4 | 6.4 | mA | 50kHz, no load, RDEL = 10k, TJ=+25°C | 5 |
| AHB, BHB Off Quiescent Current | IAHBL, IBHBL | 0.5 | 1 | 1.5 | mA | AHI = BHI = 0V, TJ=+25°C | 5 |
| AHB, BHB On Quiescent Current | IAHBH, IBHBH | 65 | 145 | 240 | µA | AHI = BHI = VDD, TJ=+25°C | 5 |
| AHB, BHB Operating Current | IAHBO, IBHBO | 0.65 | 1.1 | 1.8 | mA | f = 50kHz, CL = 1000pF, TJ=+25°C | 5 |
| AHS, BHS Leakage Current | IHLK | 1 | µA | VAHS = VBHS = 80V, VAHB = VBHB = 96, VDD = Not Connected, TJ=+25°C | 5 | ||
| VDD Rising Undervoltage Threshold | VDDUV+ | 6.8 | 7.6 | 8.25 | V | TJ=+25°C | 5 |
| VDD Falling Undervoltage Threshold | VDDUV- | 6.5 | 7.1 | 7.8 | V | TJ=+25°C | 5 |
| Undervoltage Hysteresis | UVHYS | 0.17 | 0.4 | 0.75 | V | TJ=+25°C | 5 |
| AHB, BHB Undervoltage Threshold | VHBUV | 5 | 6 | 7 | V | Referenced to AHS & BHS, TJ=+25°C | 5 |
| Low Level Input Voltage | VIL | 1 | V | Full Operating Conditions, TJ=+25°C | 5 | ||
| High Level Input Voltage | VIH | 2.5 | V | Full Operating Conditions, TJ=+25°C | 5 | ||
| Input Voltage Hysteresis | 35 | mV | 5 | ||||
| Low Level Input Current | IIL | -145 | -100 | -60 | µA | VIN = 0V, Full Operating Conditions, TJ=+25°C | 5 |
| High Level Input Current | IIH | -1 | 1 | µA | VIN = 5V, Full Operating Conditions, TJ=+25°C | 5 | |
| Dead Time | TDEAD | 2.5 | 4.5 | 8 | µs | RDEL = 100K, TJ=+25°C | 5 |
| Dead Time | TDEAD | 0.27 | 0.5 | 0.75 | µs | RDEL = 10K, TJ=+25°C | 5 |
| Low Level Output Voltage | VOL | 0.65 | 1.1 | V | IOUT = 50mA, TJ=+25°C | 6 | |
| High Level Output Voltage | VDD-VOH | 0.7 | 1.2 | V | IOUT = -50mA, TJ=+25°C | 6 | |
| Peak Pullup Current | IO+ | 1.1 | 1.4 | 2.5 | A | VOUT = 0V, TJ=+25°C | 6 |
| Peak Pulldown Current | IO- | 1 | 1.3 | 2.3 | A | VOUT = 12V, TJ=+25°C | 6 |
| Lower Turn-off Propagation Delay | TLPHL | 25 | 50 | ns | ALI-ALO, BLI-BLO, TJ=+25°C | 6 | |
| Upper Turn-off Propagation Delay | THPHL | 55 | 80 | ns | AHI-AHO, BHI-BHO, TJ=+25°C | 6 | |
| Lower Turn-on Propagation Delay | TLPLH | 40 | 85 | ns | ALI-ALO, BLI-BLO, TJ=+25°C | 6 | |
| Upper Turn-on Propagation Delay | THPLH | 75 | 110 | ns | AHI-AHO, BHI-BHO, TJ=+25°C | 6 | |
| Rise Time | TR | 9 | 20 | ns | TJ=+25°C | 6 | |
| Fall Time | TF | 9 | 20 | ns | TJ=+25°C | 6 | |
| Minimum Input Pulse Width | TPWIN-ON/OFF | 50 | ns | TJ=+25°C | 6 | ||
| Output Pulse Response to 50 ns Input Pulse | TPWOUT | 63 | 80 | ns | 6 | ||
| Disable Turn-off Propagation Delay (Lower Outputs) | TDISLOW | 50 | 80 | ns | DIS - Lower Outputs, TJ=+25°C | 6 | |
| Disable Turn-off Propagation Delay (Upper Outputs) | TDISHIGH | 75 | 100 | ns | DIS - Upper Outputs, TJ=+25°C | 6 | |
| Disable Turn-on Propagation Delay (ALO & BLO) | TDLPLH | 40 | 70 | ns | DIS - ALO & BLO, TJ=+25°C | 6 | |
| Disable Turn-on Propagation Delay (AHO & BHO) | TDHPLH | 1.2 | 2 | µs | RDEL = 10K, DIS- AHO & BHO, TJ=+25°C | 6 | |
| Refresh Pulse Width (ALO & BLO) | TREF-PW | 375 | 580 | 900 | ns | TJ=+25°C | 6 |
CAD (KiCad official)
- Symbol:
HIP4082IPZ - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: PDIP-16 (KiCad packages3D, STEP)
- 3D model files:
hip4082ipz-etched.step/hip4082ipz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hip4082ipz.step/hip4082ipz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (14 pp, sha256
9441152c4661b666, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).