component
HIP4082IBZT
Public Made by Adomby adom
RENESAS Gate Drivers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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HIP4082IBZT
RENESAS · Gate Drivers · SOIC-16
HIP4082IBZT from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BHB | power_in | High-side bootstrap supply; an external bootstrap diode and capacitor are required, with the diode cathode and the positive side of the bootstrap capacitor connected to this pin. |
| 2 | BHI | input | High-side logic input controlling the BHO driver, accepting 0V to 15V and no greater than VDD, with BLI overriding it to prevent half-bridge shoot-through. |
| 3 | BLI | input | Low-side logic input controlling the BLO driver, accepting 0V to 15V and no greater than VDD; if BHI is high or unconnected, BLI controls both BLO and BHO with dead time set at DEL. |
| 4 | ALI | input | Low-side logic input controlling the ALO driver, accepting 0V to 15V and no greater than VDD; if AHI is high or unconnected, ALI controls both ALO and AHO with dead time set at DEL. |
| 5 | DEL | passive | Turn-on delay pin; a resistor from this pin to VSS sets the timing current that defines the dead time, and the voltage across the resistor is approximately VDD - 2V. |
| 6 | VSS | power_in | Chip negative supply, generally ground; operating voltage on VSS is limited to -1.0V to +1.0V. |
| 7 | AHI | input | High-side logic input controlling the AHO driver, accepting 0V to 15V and no greater than VDD, with ALI overriding it to prevent half-bridge shoot-through. |
| 8 | DIS | input | Disable input; a high level sets all four outputs low and overrides all other inputs, accepting 0V to 15V and no greater than VDD. |
| 9 | AHB | power_in | High-side bootstrap supply; an external bootstrap diode and capacitor are required, with the diode cathode and the positive side of the bootstrap capacitor connected to this pin. |
| 10 | AHO | output | High-side gate driver output, connected to the gate of the A high-side power MOSFET. |
| 11 | AHS | power_in | High-side source connection, connected to the source of the A high-side power MOSFET and to the negative side of the bootstrap capacitor. |
| 12 | VDD | power_in | Positive supply for the control logic and lower gate drivers, operating from +8.5V to +15V and to be decoupled to VSS (pin 6). |
| 13 | ALO | output | Low-side gate driver output, connected to the gate of the A low-side power MOSFET. |
| 14 | BLO | output | Low-side gate driver output, connected to the gate of the B low-side power MOSFET. |
| 15 | BHS | power_in | High-side source connection, connected to the source of the B high-side power MOSFET and to the negative side of the bootstrap capacitor. |
| 16 | BHO | output | High-side gate driver output, connected to the gate of the B high-side power MOSFET. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-16 |
| Category | Motor Driver ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD Quiescent Current | IDD | 1.2 | 2.3 | 3.5 | mA | TJ=+25°C; All inputs = 0V, RDEL = 100K | 5 |
| VDD Quiescent Current | IDD | 2.2 | 4 | 5.5 | mA | TJ=+25°C; All inputs = 0V, RDEL = 10K | 5 |
| VDD Operating Current | IDDO | 1.5 | 2.6 | 4 | mA | TJ=+25°C; f = 50kHz, no load | 5 |
| VDD Operating Current | IDDO | 2.5 | 4 | 6.4 | mA | TJ=+25°C; 50kHz, no load, RDEL = 10k | 5 |
| AHB, BHB Off Quiescent Current | IAHBL, IBHBL | 0.5 | 1 | 1.5 | mA | TJ=+25°C; AHI = BHI = 0V | 5 |
| AHB, BHB On Quiescent Current | IAHBH, IBHBH | 65 | 145 | 240 | A | TJ=+25°C; AHI = BHI = VDD | 5 |
| AHB, BHB Operating Current | IAHBO, IBHBO | 0.65 | 1.1 | 1.8 | mA | TJ=+25°C; f = 50kHz, CL = 1000pF | 5 |
| AHS, BHS Leakage Current | IHLK | 1 | A | TJ=+25°C; VAHS = VBHS = 80V, VAHB = VBHB = 96, VDD = Not Connected | 5 | ||
| VDD Rising Undervoltage Threshold | VDDUV+ | 6.8 | 7.6 | 8.25 | V | TJ=+25°C | 5 |
| VDD Falling Undervoltage Threshold | VDDUV- | 6.5 | 7.1 | 7.8 | V | TJ=+25°C | 5 |
| Undervoltage Hysteresis | UVHYS | 0.17 | 0.4 | 0.75 | V | TJ=+25°C | 5 |
| AHB, BHB Undervoltage Threshold | VHBUV | 5 | 6 | 7 | V | TJ=+25°C; Referenced to AHS & BHS | 5 |
| Low Level Input Voltage | VIL | 1 | V | TJ=+25°C; Full Operating Conditions | 5 | ||
| High Level Input Voltage | VIH | 2.5 | V | TJ=+25°C; Full Operating Conditions | 5 | ||
| Input Voltage Hysteresis | 35 | mV | TJ=+25°C | 5 | |||
| Low Level Input Current | IIL | -145 | -100 | -60 | A | TJ=+25°C; VIN = 0V, Full Operating Conditions | 5 |
| High Level Input Current | IIH | -1 | 1 | A | TJ=+25°C; VIN = 5V, Full Operating Conditions | 5 | |
| Dead Time | TDEAD | 2.5 | 4.5 | 8 | s | TJ=+25°C; RDEL = 100K | 5 |
| Dead Time | TDEAD | 0.27 | 0.5 | 0.75 | s | TJ=+25°C; RDEL = 10K | 5 |
| Low Level Output Voltage | VOL | 0.65 | 1.1 | V | TJ=+25°C; IOUT = 50mA | 6 | |
| High Level Output Voltage | VDD-VOH | 0.7 | 1.2 | V | TJ=+25°C; IOUT = -50mA | 6 | |
| Peak Pullup Current | IO+ | 1.1 | 1.4 | 2.5 | A | TJ=+25°C; VOUT = 0V | 6 |
| Peak Pulldown Current | IO- | 1 | 1.3 | 2.3 | A | TJ=+25°C; VOUT = 12V | 6 |
| Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) | TLPHL | 25 | 50 | ns | TJ=+25°C | 6 | |
| Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) | THPHL | 55 | 80 | ns | TJ=+25°C | 6 | |
| Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) | TLPLH | 40 | 85 | ns | TJ=+25°C | 6 | |
| Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) | THPLH | 75 | 110 | ns | TJ=+25°C | 6 | |
| Rise Time | TR | 9 | 20 | ns | TJ=+25°C | 6 | |
| Fall Time | TF | 9 | 20 | ns | TJ=+25°C | 6 | |
| Minimum Input Pulse Width | TPWIN-ON/OFF | 50 | ns | TJ=+25°C | 6 | ||
| Output Pulse Response to 50 ns Input Pulse | TPWOUT | 63 | 80 | ns | TJ=+25°C; 50 ns input pulse | 6 | |
| Disable Turn-off Propagation Delay (DIS - Lower Outputs) | TDISLOW | 50 | 80 | ns | TJ=+25°C | 6 | |
| Disable Turn-off Propagation Delay (DIS - Upper Outputs) | TDISHIGH | 75 | 100 | ns | TJ=+25°C | 6 | |
| Disable Turn-on Propagation Delay (DIS - ALO & BLO) | TDLPLH | 40 | 70 | ns | TJ=+25°C | 6 | |
| Disable Turn-on Propagation Delay (DIS - AHO & BHO) | TDHPLH | 1.2 | 2 | s | TJ=+25°C; RDEL = 10K | 6 | |
| Refresh Pulse Width (ALO & BLO) | TREF-PW | 375 | 580 | 900 | ns | TJ=+25°C | 6 |
| Supply Voltage | VDD | -0.3 | 16 | V | 5 | ||
| Logic I/O Voltages | -0.3 | V | Maximum printed as VDD +0.3V | 5 | |||
| Voltage on AHS, BHS | -6 | 80 | V | Min is transient; max for 25°C to 150°C | 5 | ||
| Voltage on AHS, BHS | -6 | 70 | V | Min is transient; max for -55°C to 150°C | 5 | ||
| Voltage on AHB, BHB | -0.3 | V | Referenced to VAHS, BHS; max printed as VAHS, BHS +VDD | 5 | |||
| Voltage on ALO, BLO | -0.3 | V | Referenced to VSS; max printed as VDD +0.3V | 5 | |||
| Voltage on AHO, BHO | -0.3 | V | Referenced to VAHS, BHS; max printed as VAHB, BHB +0.3V | 5 | |||
| Input Current, DEL | -5 | 0 | mA | 5 | |||
| Phase Slew Rate | 20 | V/ns | 5 | ||||
| Storage Temperature Range | -65 | 150 | °C | 5 | |||
| Operating Max. Junction Temperature | 150 | °C | 5 | ||||
| Lead Temperature (Soldering 10s) | 300 | °C | Soldering 10s (for SOIC, lead tips only) | 5 | |||
| Supply Voltage | VDD | 8.5 | 15 | V | 5 | ||
| Voltage on VSS | VSS | -1 | 1 | V | 5 | ||
| Voltage on AHB, BHB | 7.5 | V | Referenced to VAHS, BHS; max printed as VAHS, BHS +VDD | 5 | |||
| Input Current, DEL | -4 | mA | Max printed as -100A | 5 | |||
| Input Current, DEL | -100 | A | Printed as -100A (unit as printed) | 5 | |||
| Thermal Resistance (Junction to Ambient), SOIC Package | θJA | 115 | °C/W | SOIC package | 5 | ||
| VDD Rising Undervoltage Threshold | VDDUV+ | 6.5 | 8.5 | V | TJ = -55°C to +150°C | 5 | |
| VDD Falling Undervoltage Threshold | VDDUV- | 6.25 | 8.1 | V | TJ = -55°C to +150°C | 5 | |
| Undervoltage Hysteresis | UVHYS | 0.15 | 0.9 | V | TJ = -55°C to +150°C | 5 | |
| AHB, BHB Undervoltage Threshold | VHBUV | 4.5 | 7.5 | V | TJ = -55°C to +150°C; Referenced to AHS & BHS | 5 | |
| Low Level Input Voltage | VIL | 0.8 | V | TJ = -55°C to +150°C; Full Operating Conditions | 5 | ||
| High Level Input Voltage | VIH | 2.7 | V | TJ = -55°C to +150°C; Full Operating Conditions | 5 |
CAD (KiCad official)
- Symbol:
HIP4082IBZT - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
hip4082ibzt-etched.step/hip4082ibzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hip4082ibzt.step/hip4082ibzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (15 pp, sha256
c885d440e42c4e2c, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).