component

HIP4082IBZ

Public Made by Adom

by adom

RENESAS Pre-ordered Chips, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icship4082ibzfactory-2.0.0extractor-text

Verified HIP4082IBZ

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: HIP4082IBZ · SOIC-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 14-page datasheet
  • ✓distributor: lcsc C1549293, digikey HIP4082IBZ-ND, mouser 968-HIP4082IBZ
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-bliirc3k/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ hip4082ibz.kicad_sym✓ hip4082ibz.kicad_mod✓ hip4082ibz.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers hip4082ibz: viewers · Ray 7d ago
hip4082ibz-etched.glb Publish 0.1.0 · Ray 7d ago
hip4082ibz-etched.step hip4082ibz: factory component page (tier=mfr) · Ray 7d ago
hip4082ibz-hero.glb hip4082ibz: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
hip4082ibz-hero.overlay.json Publish 0.1.0 · Ray 7d ago
hip4082ibz.glb Publish 0.1.0 · Ray 7d ago
hip4082ibz.kicad_mod Publish 0.1.0 · Ray 7d ago
hip4082ibz.kicad_sym Publish 0.1.0 · Ray 7d ago
hip4082ibz.lbr Publish 0.1.0 · Ray 7d ago
hip4082ibz.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago
verification.json Verified: Published by the parts factory: tier mfr, 16 pins · Ray 7d ago

HIP4082IBZ

RENESAS · Pre-ordered Chips · SOIC-16

HIP4082IBZ from RENESAS, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BHB power_in High-side bootstrap supply that requires an external bootstrap diode and capacitor, with the diode cathode and positive capacitor side connected to this pin.
2 BHI input High-side input controlling the BHO driver, accepting 0V to 15V logic levels no greater than VDD.
3 BLI input Low-side input controlling the BLO driver, accepting 0V to 15V logic levels no greater than VDD.
4 ALI input Low-side input controlling the ALO driver, accepting 0V to 15V logic levels no greater than VDD.
5 DEL passive Turn-on delay pin where a resistor to VSS sets the dead time, with the voltage across the resistor approximately VDD -2V.
6 VSS power_in Chip negative supply, generally ground, to which VDD must be decoupled.
7 AHI input High-side input controlling the AHO driver, accepting 0V to 15V logic levels no greater than VDD.
8 DIS input Disable input that when taken high sets all four outputs low and overrides all other inputs, accepting 0V to 15V no greater than VDD.
9 AHB power_in High-side bootstrap supply that requires an external bootstrap diode and capacitor, with the diode cathode and positive capacitor side connected to this pin.
10 AHO output High-side gate driver output that connects to the gate of the A high-side power MOSFET.
11 AHS passive High-side source connection to the A high-side MOSFET source, which also receives the negative side of the bootstrap capacitor.
12 VDD power_in Positive supply for control logic and lower gate drivers, specified at 8.5V to 15V and decoupled to VSS.
13 ALO output Low-side gate driver output that connects to the gate of the A low-side power MOSFET.
14 BLO output Low-side gate driver output that connects to the gate of the B low-side power MOSFET.
15 BHS passive High-side source connection to the B high-side MOSFET source, which also receives the negative side of the bootstrap capacitor.
16 BHO output High-side gate driver output that connects to the gate of the B high-side power MOSFET.

Key specifications

Parameter Value
Manufacturer RENESAS
Package SOIC-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Quiescent Current IDD 1.2 2.3 3.5 mA All inputs = 0V, RDEL = 100K; TJ = +25°C 5
VDD Quiescent Current IDD 0.85 4 mA All inputs = 0V, RDEL = 100K; TJ = -55 to +150°C 5
VDD Quiescent Current IDD 2.2 4 5.5 mA All inputs = 0V, RDEL = 10K; TJ = +25°C 5
VDD Quiescent Current IDD 1.9 6 mA All inputs = 0V, RDEL = 10K; TJ = -55 to +150°C 5
VDD Operating Current IDDO 1.5 2.6 4 mA f = 50kHz, no load; TJ = +25°C 5
VDD Operating Current IDDO 1.1 4.2 mA f = 50kHz, no load; TJ = -55 to +150°C 5
AHB, BHB Off Quiescent Current IAHBL, IBHBL 0.5 1 1.5 mA AHI = BHI = 0V; TJ = +25°C 5
AHB, BHB Off Quiescent Current IAHBL, IBHBL 0.4 1.6 mA AHI = BHI = 0V; TJ = -55 to +150°C 5
AHB, BHB On Quiescent Current IAHBH, IBHBH 65 145 240 µA AHI = BHI = VDD; TJ = +25°C 5
AHB, BHB On Quiescent Current IAHBH, IBHBH 40 250 µA AHI = BHI = VDD; TJ = -55 to +150°C 5
AHB, BHB Operating Current IAHBO, IBHBO 0.65 1.1 1.8 mA f = 50kHz, CL = 1000pF; TJ = +25°C 5
AHS, BHS Leakage Current IHLK 1 µA VAHS = VBHS = 80V, VAHB = VBHB = 96, VDD = Not Connected 5
VDD Rising Undervoltage Threshold VDDUV+ 6.8 7.6 8.25 V TJ = +25°C 5
VDD Rising Undervoltage Threshold VDDUV+ 6.5 8.5 V TJ = -55 to +150°C 5
VDD Falling Undervoltage Threshold VDDUV- 6.5 7.1 7.8 V TJ = +25°C 5
VDD Falling Undervoltage Threshold VDDUV- 6.25 8.1 V TJ = -55 to +150°C 5
Undervoltage Hysteresis UVHYS 0.17 0.4 0.75 V TJ = +25°C 5
Undervoltage Hysteresis UVHYS 0.15 0.9 V TJ = -55 to +150°C 5
AHB, BHB Undervoltage Threshold VHBUV 5 6 7 V Referenced to AHS & BHS; TJ = +25°C 5
AHB, BHB Undervoltage Threshold VHBUV 4.5 7.5 V Referenced to AHS & BHS; TJ = -55 to +150°C 5
Low Level Input Voltage VIL 1 V Full Operating Conditions; TJ = +25°C 5
Low Level Input Voltage VIL 0.8 V Full Operating Conditions; TJ = -55 to +150°C 5
High Level Input Voltage VIH 2.5 V Full Operating Conditions; TJ = +25°C 5
High Level Input Voltage VIH 2.7 V Full Operating Conditions; TJ = -55 to +150°C 5
Input Voltage Hysteresis 35 mV 5
Low Level Input Current IIL -145 -100 -60 µA VIN = 0V, Full Operating Conditions; TJ = +25°C 5
Low Level Input Current IIL -150 -50 µA VIN = 0V, Full Operating Conditions; TJ = -55 to +150°C 5
High Level Input Current IIH -1 1 µA VIN = 5V, Full Operating Conditions; TJ = +25°C 5
High Level Input Current IIH -10 10 µA VIN = 5V, Full Operating Conditions; TJ = -55 to +150°C 5
Dead Time TDEAD 2.5 4.5 8 s RDEL = 100K; TJ = +25°C 5
Dead Time TDEAD 2 8.5 s RDEL = 100K; TJ = -55 to +150°C 5
Dead Time TDEAD 0.27 0.5 0.75 s RDEL = 10K; TJ = +25°C 5
Dead Time TDEAD 0.2 0.85 s RDEL = 10K; TJ = -55 to +150°C 5
Low Level Output Voltage VOL 0.65 1.1 V IOUT = 50mA; TJ = +25°C 6
Low Level Output Voltage VOL 0.5 1.2 V IOUT = 50mA; TJ = -55 to +150°C 6
High Level Output Voltage VDD-VOH 0.7 1.2 V IOUT = -50mA; TJ = +25°C 6
High Level Output Voltage VDD-VOH 0.5 1.3 V IOUT = -50mA; TJ = -55 to +150°C 6
Peak Pullup Current IO+ 1.4 2.5 A VOUT = 0V; TJ = +25°C 6
Peak Pullup Current IO+ 0.85 2.75 A VOUT = 0V; TJ = -55 to +150°C 6
Peak Pulldown Current IO- 1.3 2.3 A VOUT = 12V; TJ = +25°C 6
Peak Pulldown Current IO- 0.75 2.5 A VOUT = 12V; TJ = -55 to +150°C 6
Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) TLPHL 25 50 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) THPHL 55 80 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) TLPLH 40 85 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) THPLH 75 110 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Rise Time TR 9 20 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Fall Time TF 9 20 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Minimum Input Pulse Width TPWIN-ON/OFF 50 ns TJ = +25°C 6
Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW 50 80 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH 75 100 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Disable Turn-on Propagation Delay (DIS - ALO & BLO) TDLPLH 40 70 ns VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF; TJ = +25°C 6
Disable Turn-on Propagation Delay (DIS - AHO & BHO) TDHPLH 1.2 2 s RDEL = 10K; TJ = +25°C 6
Refresh Pulse Width (ALO & BLO) TREF-PW 375 580 900 ns TJ = +25°C 6
Refresh Pulse Width (ALO & BLO) TREF-PW 350 950 ns TJ = -55 to +150°C 6
Supply Voltage VDD -0.3 16 V 5
Voltage on AHS, BHS VAHS, VBHS -6 80 V Transient to 80V; 25°C to 150°C 5
Voltage on AHS, BHS VAHS, VBHS -6 70 V Transient; -55°C to 150°C 5
Input Current, DEL IDEL -5 0 mA 5
Phase Slew Rate 20 V/ns 5
Storage Temperature Range -65 150 °C 5
Operating Max. Junction Temperature 150 °C 5
Lead Temperature (Soldering 10s) 300 °C 10s, for SOIC lead tips only 5
Supply Voltage VDD 8.5 15 V 5
Voltage on VSS VSS -1 1 V 5
Voltage on AHB, BHB VAHB, VBHB 7.5 V Referenced to VAHS, BHS; upper limit VAHS, BHS +VDD 5
Thermal Resistance JA θJA 115 °C/W SOIC package 5

CAD (KiCad official)

  • Symbol: HIP4082IBZ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hip4082ibz-etched.step / hip4082ibz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hip4082ibz.step / hip4082ibz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: RENESAS datasheet (14 pp, sha256 9441152c4661b666, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF