component
HIP4081AIBZT
Public Made by Adomby adom
Intersil(Renesas Electronics) Gate Drive ICs, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownHIP4081AIBZT
Intersil(Renesas Electronics) · Gate Drive ICs · SOIC-20-300mil
HIP4081AIBZT from Intersil(Renesas Electronics), in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BHB | power_in | B high-side bootstrap supply; connect bootstrap diode cathode and bootstrap capacitor positive side here, internal charge pump supplies 30µA and clamps to approximately 12.8V. |
| 2 | BHI | input | B high-side logic input controlling BHO; overridden by BLI high and DIS high, drivable from 0V to 15V (no greater than VDD). |
| 3 | DIS | input | Disable input; when high sets all four outputs low and overrides all other inputs, drivable from 0V to 15V (no greater than VDD). |
| 4 | VSS | power_in | Chip negative supply, generally ground. |
| 5 | BLI | input | B low-side logic input controlling BLO; if BHI is high or not connected BLI controls both BLO and BHO with dead time set by HDEL and LDEL, drivable from 0V to 15V (no greater than VDD). |
| 6 | ALI | input | A low-side logic input controlling ALO; if AHI is high or not connected ALI controls both ALO and AHO with dead time set by HDEL and LDEL, drivable from 0V to 15V (no greater than VDD). |
| 7 | AHI | input | A high-side logic input controlling AHO; overridden by ALI high and DIS high, drivable from 0V to 15V (no greater than VDD). |
| 8 | HDEL | passive | High-side turn-on delay; connect resistor to VSS to set turn-on delay of both high-side drivers, reference voltage approximately 5.1V. |
| 9 | LDEL | passive | Low-side turn-on delay; connect resistor to VSS to set turn-on delay of both low-side drivers, reference voltage approximately 5.1V. |
| 10 | AHB | power_in | A high-side bootstrap supply; connect bootstrap diode cathode and bootstrap capacitor positive side here, internal charge pump supplies 30µA and clamps to approximately 12.8V. |
| 11 | AHO | output | A high-side output; connect to gate of A high-side power MOSFET. |
| 12 | AHS | passive | A high-side source connection; connect to source of A high-side power MOSFET and negative side of bootstrap capacitor. |
| 13 | ALO | output | A low-side output; connect to gate of A low-side power MOSFET. |
| 14 | ALS | passive | A low-side source connection; connect to source of A low-side power MOSFET. |
| 15 | VCC | power_in | Positive supply to gate drivers; must be same potential as VDD and connected to anodes of two bootstrap diodes. |
| 16 | VDD | power_in | Positive supply to lower gate drivers; must be same potential as VCC and decoupled to VSS. |
| 17 | BLS | passive | B low-side source connection; connect to source of B low-side power MOSFET. |
| 18 | BLO | output | B low-side output; connect to gate of B low-side power MOSFET. |
| 19 | BHS | passive | B high-side source connection; connect to source of B high-side power MOSFET and negative side of bootstrap capacitor. |
| 20 | BHO | output | B high-side output; connect to gate of B high-side power MOSFET. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Intersil(Renesas Electronics) |
| Package | SOIC-20-300mil |
| Category | Power Management ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VDD and VCC (abs max) | VDD, VCC | -0.3 | 16 | V | relative to VSS | 4 | |
| Voltage on AHS, BHS (25°C to 125°C) | VAHS, VBHS | -6 | 80 | V | -6.0V transient; 25°C to 125°C | 4 | |
| Voltage on AHS, BHS (-55°C to 125°C) | VAHS, VBHS | -6 | 70 | V | -6.0V transient; -55°C to 125°C | 4 | |
| Voltage on ALS, BLS (abs max) | VALS, VBLS | -2 | 2 | V | transient | 4 | |
| Input Current, HDEL and LDEL (abs max) | -5 | 0 | mA | 4 | |||
| Phase Slew Rate | 20 | V/ns | 4 | ||||
| Storage Temperature Range | -65 | 150 | °C | 4 | |||
| Operating Max. Junction Temperature | TJ | 125 | °C | 4 | |||
| Lead Temperature (Soldering 10s) | 300 | °C | SOIC lead tips only | 4 | |||
| Thermal Resistance Junction-Ambient, SOIC | θJA | 85 | °C/W | typical; mounted on evaluation PC board in free air | 4 | ||
| Supply Voltage VDD and VCC (operating) | VDD, VCC | 9.5 | 15 | V | 4 | ||
| Voltage on ALS, BLS (operating) | VALS, VBLS | -1 | 1 | V | 4 | ||
| Voltage on AHB, BHB (operating) | VAHB, VBHB | 5 | 15 | V | relative to VAHS, BHS: VAHS,BHS +5V to +15V | 4 | |
| Input Current, HDEL and LDEL (operating) | -500 | -50 | µA | 4 | |||
| Operating Ambient Temperature Range | TA | -40 | 85 | °C | 4 | ||
| VDD Quiescent Current | IDD | 8.5 | 10.5 | 14.5 | mA | All inputs = 0V; TJ=25°C | 4 |
| VDD Quiescent Current (full temp) | IDD | 7.5 | 14.5 | mA | All inputs = 0V; TJS=-40°C to 125°C | 4 | |
| VDD Operating Current | IDDO | 9.5 | 12.5 | 15.5 | mA | Outputs switching f = 500kHz; TJ=25°C | 4 |
| VDD Operating Current (full temp) | IDDO | 8.5 | 15.5 | mA | Outputs switching f = 500kHz; TJS=-40°C to 125°C | 4 | |
| VCC Quiescent Current | ICC | 0.1 | 10 | µA | All Inputs = 0V, IALO = IBLO = 0; TJ=25°C | 4 | |
| VCC Quiescent Current (full temp) | ICC | 20 | µA | All Inputs = 0V, IALO = IBLO = 0; TJS=-40°C to 125°C | 4 | ||
| VCC Operating Current | ICCO | 1 | 1.25 | 2 | mA | f = 500kHz, No Load; TJ=25°C | 4 |
| AHB, BHB Quiescent Current - Qpump Output Current | IAHB, IBHB | -50 | -30 | -11 | µA | All Inputs = 0V, IAHO = IBHO = 0, VDD = VCC = VAHB = VBHB = 10V; TJ=25°C | 4 |
| AHB, BHB Operating Current | IAHBO, IBHBO | 0.6 | 1.2 | 1.5 | mA | f = 500kHz, No Load; TJ=25°C | 4 |
| AHS, BHS, AHB, BHB Leakage Current | IHLK | 0.02 | 1 | µA | VBHS = VAHS = 80V, VAHB = VBHB = 93V; TJ=25°C | 4 | |
| AHB-AHS, BHB-BHS Qpump Output Voltage | VAHB-VAHS, VBHB-VBHS | 11.5 | 12.6 | 14 | V | IAHB = IAHB = 0, No Load; TJ=25°C | 4 |
| Low Level Input Voltage | VIL | 1 | V | Full Operating Conditions; TJ=25°C | 4 | ||
| Low Level Input Voltage (full temp) | VIL | 0.8 | V | Full Operating Conditions; TJS=-40°C to 125°C | 4 | ||
| High Level Input Voltage | VIH | 2.5 | V | Full Operating Conditions; TJ=25°C | 4 | ||
| High Level Input Voltage (full temp) | VIH | 2.7 | V | Full Operating Conditions; TJS=-40°C to 125°C | 4 | ||
| Input Voltage Hysteresis | 35 | mV | TJ=25°C | 4 | |||
| Low Level Input Current | IIL | -130 | -100 | -75 | µA | VIN = 0V, Full Operating Conditions; TJ=25°C | 4 |
| Low Level Input Current (full temp) | IIL | -135 | -65 | µA | VIN = 0V, Full Operating Conditions; TJS=-40°C to 125°C | 4 | |
| High Level Input Current | IIH | -1 | 1 | µA | VIN = 5V, Full Operating Conditions; TJ=25°C | 4 | |
| LDEL, HDEL Voltage | VHDEL, VLDEL | 4.9 | 5.1 | 5.3 | V | IHDEL = ILDEL = -100µA; TJ=25°C | 4 |
| Low Level Output Voltage | VOL | 0.7 | 0.85 | 1 | V | IOUT = 100mA; TJ=25°C | 4 |
| Low Level Output Voltage (full temp) | VOL | 0.5 | 1.1 | V | IOUT = 100mA; TJS=-40°C to 125°C | 4 | |
| High Level Output Voltage | VCC-VOH | 0.8 | 0.95 | 1.1 | V | IOUT = -100mA; TJ=25°C | 4 |
| High Level Output Voltage (full temp) | VCC-VOH | 0.5 | 1.2 | V | IOUT = -100mA; TJS=-40°C to 125°C | 4 | |
| Peak Pullup Current | IO+ | 1.7 | 2.6 | 3.8 | A | VOUT = 0V; TJ=25°C | 4 |
| Peak Pulldown Current | IO- | 1.7 | 2.4 | 3.3 | A | VOUT = 12V; TJ=25°C | 5 |
| Undervoltage, Rising Threshold | UV+ | 8.1 | 8.8 | 9.4 | V | TJ=25°C | 5 |
| Undervoltage, Rising Threshold (full temp) | UV+ | 8 | 9.5 | V | TJS=-40°C to 125°C | 5 | |
| Undervoltage, Falling Threshold | UV- | 7.6 | 8.3 | 8.9 | V | TJ=25°C | 5 |
| Undervoltage, Falling Threshold (full temp) | UV- | 7.5 | 9 | V | TJS=-40°C to 125°C | 5 | |
| Undervoltage, Hysteresis | HYS | 0.25 | 0.4 | 0.65 | V | TJ=25°C | 5 |
| Lower Turn-off Propagation Delay | TLPHL | 30 | 60 | ns | ALI-ALO, BLI-BLO; RHDEL = RLDEL = 10K, CL = 1000pF; TJ=25°C | 5 | |
| Upper Turn-off Propagation Delay | THPHL | 35 | 70 | ns | AHI-AHO, BHI-BHO; RHDEL = RLDEL = 10K, CL = 1000pF; TJ=25°C | 5 | |
| Lower Turn-on Propagation Delay | TLPLH | 45 | 70 | ns | ALI-ALO, BLI-BLO; RHDEL = RLDEL = 10K; TJ=25°C | 5 | |
| Upper Turn-on Propagation Delay | THPLH | 60 | 90 | ns | AHI-AHO, BHI-BHO; RHDEL = RLDEL = 10K; TJ=25°C | 5 | |
| Rise Time | TR | 10 | 25 | ns | CL = 1000pF; TJ=25°C | 5 | |
| Fall Time | TF | 10 | 25 | ns | CL = 1000pF; TJ=25°C | 5 | |
| Turn-on Input Pulse Width | TPWIN-ON | 50 | ns | RHDEL = RLDEL = 10K; TJ=25°C | 5 | ||
| Turn-off Input Pulse Width | TPWIN-OFF | 40 | ns | RHDEL = RLDEL = 10K; TJ=25°C | 5 | ||
| Turn-on Output Pulse Width | TPWOUT-ON | 40 | ns | RHDEL = RLDEL = 10K; TJ=25°C | 5 | ||
| Turn-off Output Pulse Width | TPWOUT-OFF | 30 | ns | RHDEL = RLDEL = 10K; TJ=25°C | 5 | ||
| Disable Turn-off Propagation Delay (Lower Outputs) | TDISLOW | 45 | 75 | ns | DIS - Lower Outputs; TJ=25°C | 5 | |
| Disable Turn-off Propagation Delay (Upper Outputs) | TDISHIGH | 55 | 85 | ns | DIS - Upper Outputs; TJ=25°C | 5 | |
| Disable to Lower Turn-on Propagation Delay | TDLPLH | 40 | 70 | ns | DIS - ALO and BLO; TJ=25°C | 5 | |
| Refresh Pulse Width (ALO and BLO) | TREF-PW | 240 | 410 | 550 | ns | TJ=25°C | 5 |
| Disable to Upper Enable | TUEN | 450 | 620 | ns | DIS - AHO and BHO; TJ=25°C | 5 |
CAD (KiCad official)
- Symbol:
HIP4081AIBZT - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
hip4081aibzt-etched.step/hip4081aibzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hip4081aibzt.step/hip4081aibzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Intersil(Renesas Electronics) datasheet (17 pp, sha256
9712192314428f32, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).