# Hi9102

**Hichips(智芯)** · DC-DC Converters · ESOP-8

Hi9102 from Hichips(智芯), in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | D | passive | Drain of the internal power MOSFET; the Hi9102 absolute maximum rating for this pin is -0.3 to 60 V. |
| 2 | VDD | power_in | Supply input that must stay between 6.5 V and 24 V for normal operation (UVLO 3.5 V, internal clamp 24 V), with a bypass capacitor of at least 10 µF to GND placed close to the pin. |
| 3 | NC | unconnected | No internal connection; leave unconnected. |
| 4 | FB | input | Output voltage sense input with a reference of 1.16 V typical (1.125 to 1.195 V), absolute maximum -0.3 to 6 V, set by the R3/R4 divider. |
| 5 | GND | power_in | Chip ground, which should be kept single-point connected with the VDD capacitor ground and the current-sense resistor ground. |
| 6 | NC | unconnected | No internal connection; leave unconnected. |
| 7 | NC | unconnected | No internal connection; leave unconnected. |
| 8 | CS | input | Current sense input with a 200 mV reference (190 to 210 mV), absolute maximum -0.3 to 40 V, where the sense resistor sets the maximum output current as I = 0.2 V / Rcs. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Hichips(智芯) |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply input voltage | VDD | -0.3 |  | 40 | V |  | 3 |
| CS pin withstand voltage | CS | -0.3 |  | 40 | V |  | 3 |
| Built-in power MOS drain voltage (Hi9102) | D | -0.3 |  | 60 | V | Hi9102 variant | 3 |
| FB output voltage sampling pin | FB | -0.3 |  | 6 | V |  | 3 |
| Storage temperature | TSTG | -40 |  | 150 | ℃ |  | 3 |
| Operating temperature | TA | -40 |  | 125 | ℃ |  | 3 |
| ESD HBM human body model | ESD | 2 |  |  | KV | HBM human body discharge mode; printed as >2 KV | 3 |
| Start-up current | ISTART | 10 |  |  | uA |  | 7 |
| VDD voltage range | VDD | 6.5 |  | 24 | V |  | 7 |
| Current limit voltage | VCS |  |  | 400 | mV | VIN=6.5V | 7 |
| Current detection reference voltage | VREF | 190 | 200 | 210 | mV |  | 7 |
| Output sampling reference voltage | VFB | 1.125 | 1.16 | 1.195 | V |  | 7 |

## CAD (KiCad official)

- Symbol: `Hi9102`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `hi9102-etched.step` / `hi9102-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hi9102.step` / `hi9102.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Hichips(智芯) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757759474717339648) (14 pp, sha256 `38e48b4d3258692c`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hi9102-datasheet.pdf)