component
Hi9100
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Hichips(智芯) DC-DC Converters, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Hi9100
Hichips(智芯) · DC-DC Converters · SOT-23-5
Hi9100 from Hichips(智芯), in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRV | output | Drives the gate of the external power MOSFET, with pull-up current of 400 mA and pull-down current of 600 mA (typ.) per the electrical characteristics. |
| 2 | GND | power_in | Chip ground; per the PCB guidance, it should be tied at a single point together with the VDD capacitor ground and the CS sense-resistor ground. |
| 3 | CS | input | Current-sense input for peak-current limiting and setting the maximum output current via a resistor to GND, with a 200 mV reference (VCS limit 400 mV max) and a CS pin rating of -0.3 to 40 V. |
| 4 | FB | input | Output-voltage sense input connected to the resistor divider, with a typical 1.16 V reference (1.125-1.195 V) and an absolute maximum rating of -0.3 to 6 V. |
| 5 | VDD | power_in | Supply input that starts operation above 6.5 V, with UVLO at 3.5 V, an internal clamp of 24 V max (absolute maximum -0.3 to 40 V), and a bypass capacitor of at least 10 uF required. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hichips(智芯) |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 启动电流 (Start-up current) | ISTART | 10 | uA | 7 | |||
| VDD 电压范围 (VDD voltage range) | VDD | 6.5 | 24 | V | 7 | ||
| 限流电压 (Current limit voltage) | VCS | 400 | mV | VIN=6.5V | 7 | ||
| 电流检测基准电压 (Current sense reference voltage) | VREF | 190 | 200 | 210 | mV | 7 | |
| 输出采样基准电压 (Output sampling reference voltage) | VFB | 1.125 | 1.16 | 1.195 | V | 7 | |
| VDD 极限电压 (VDD absolute maximum voltage) | VDD | -0.3 | 40 | V | 3 | ||
| CS 管脚耐压 (CS pin voltage) | CS | -0.3 | 40 | V | 3 | ||
| FB 输出电压采样 (FB pin voltage) | FB | -0.3 | 6 | V | 3 | ||
| 存储温度 (Storage temperature) | TSTG | -40 | 150 | ℃ | 3 | ||
| 工作温度 (Operating temperature) | TA | -40 | 125 | ℃ | 3 | ||
| ESD HBM 人体放电模式 (ESD, human body model) | ESD | 2 | KV | HBM; datasheet prints '>2 KV' | 3 |
CAD (KiCad official)
- Symbol:
Hi9100 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
hi9100-etched.step/hi9100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hi9100.step/hi9100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Hichips(智芯) datasheet (14 pp, sha256
38e48b4d3258692c, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# Hi9100
**Hichips(智芯)** · DC-DC Converters · SOT-23-5
Hi9100 from Hichips(智芯), in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DRV | output | Drives the gate of the external power MOSFET, with pull-up current of 400 mA and pull-down current of 600 mA (typ.) per the electrical characteristics. |
| 2 | GND | power_in | Chip ground; per the PCB guidance, it should be tied at a single point together with the VDD capacitor ground and the CS sense-resistor ground. |
| 3 | CS | input | Current-sense input for peak-current limiting and setting the maximum output current via a resistor to GND, with a 200 mV reference (VCS limit 400 mV max) and a CS pin rating of -0.3 to 40 V. |
| 4 | FB | input | Output-voltage sense input connected to the resistor divider, with a typical 1.16 V reference (1.125-1.195 V) and an absolute maximum rating of -0.3 to 6 V. |
| 5 | VDD | power_in | Supply input that starts operation above 6.5 V, with UVLO at 3.5 V, an internal clamp of 24 V max (absolute maximum -0.3 to 40 V), and a bypass capacitor of at least 10 uF required. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Hichips(智芯) |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 启动电流 (Start-up current) | ISTART | 10 | | | uA | | 7 |
| VDD 电压范围 (VDD voltage range) | VDD | 6.5 | | 24 | V | | 7 |
| 限流电压 (Current limit voltage) | VCS | | | 400 | mV | VIN=6.5V | 7 |
| 电流检测基准电压 (Current sense reference voltage) | VREF | 190 | 200 | 210 | mV | | 7 |
| 输出采样基准电压 (Output sampling reference voltage) | VFB | 1.125 | 1.16 | 1.195 | V | | 7 |
| VDD 极限电压 (VDD absolute maximum voltage) | VDD | -0.3 | | 40 | V | | 3 |
| CS 管脚耐压 (CS pin voltage) | CS | -0.3 | | 40 | V | | 3 |
| FB 输出电压采样 (FB pin voltage) | FB | -0.3 | | 6 | V | | 3 |
| 存储温度 (Storage temperature) | TSTG | -40 | | 150 | ℃ | | 3 |
| 工作温度 (Operating temperature) | TA | -40 | | 125 | ℃ | | 3 |
| ESD HBM 人体放电模式 (ESD, human body model) | ESD | 2 | | | KV | HBM; datasheet prints '>2 KV' | 3 |
## CAD (KiCad official)
- Symbol: `Hi9100`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `hi9100-etched.step` / `hi9100-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hi9100.step` / `hi9100.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Hichips(智芯) datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757759478488018944) (14 pp, sha256 `38e48b4d3258692c`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/hi9100-datasheet.pdf)