# HGC5615CM

**HGSEMI** · Digital To Analog Converters (DACs) · SOP-8

HGC5615CM from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DIN | input | Serial data input; data is clocked in most significant bit first on the rising edge of SCLK while CS is low. |
| 2 | SCLK | input | Serial clock input; the rising edge shifts data into the input register, and the clock should be held low when CS is high. |
| 3 | CS | input | Active-low chip select; the rising edge of CS transfers the shift-register data to the DAC register, and CS transitions should occur while SCLK is low. |
| 4 | DOUT | output | Serial data output for daisy chaining, delayed by 16 clock cycles plus one clock width from DIN. |
| 5 | AGND | power_in | Analog ground; the datasheet recommends connecting it to the system analog ground plane. |
| 6 | REFIN | input | Reference input, buffered with high impedance, which sets the DAC full-scale output (output range is 2 times the reference voltage). |
| 7 | OUT | output | DAC analog voltage output from a rail-to-rail buffer amplifier with fixed gain of 2. |
| 8 | VDD | power_in | Positive power supply, specified at 5 V nominal (4.5 V to 5.5 V) in the recommended operating conditions. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (VDD to AGND) | VDD |  |  | 7 | V | over operating free-air temperature range | 4 |
| Digital input voltage range to AGND |  | -0.3 |  |  | V | max printed as VDD + 0.3 V | 4 |
| Reference input voltage range to AGND |  | -0.3 |  |  | V | max printed as VDD + 0.3 V | 4 |
| Continuous current at any terminal |  |  |  | 20 | mA |  | 4 |
| Operating free-air temperature range, TA (HGC5615C grade) | TA | 0 |  | 70 | °C | HGC5615C grade (the C grade applies to the CM suffix) | 4 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 4 |
| Lead temperature |  |  |  | 260 | °C | 1.6 mm (1/16 inch) from case for 10 s | 4 |
| Supply voltage, VDD (recommended) | VDD | 4.5 | 5 | 5.5 | V |  | 4 |
| High-level digital input voltage | VIH | 2.4 |  |  | V |  | 4 |
| Low-level digital input voltage | VIL |  |  | 0.8 | V |  | 4 |
| Reference voltage, Vref to REFIN terminal | Vref | 2 | 2.048 |  | V | max printed as VDD-2 V | 4 |
| Load resistance | RL | 2 |  |  | kΩ |  | 4 |
| Operating free-air temperature, TA (HGC5615C) | TA | 0 |  | 70 | °C | HGC5615C grade | 4 |
| Integral nonlinearity, end point adjusted (INL) | INL | -1 |  | 1 | LSB | Vref=2.048V; tested code 3 to 1024 | 5 |
| Differential nonlinearity (DNL) | DNL | -0.5 | 0.1 | 0.5 | LSB | Vref=2.048V | 5 |
| Zero-scale error (offset error at zero scale) | EZS | -3 |  | 3 | LSB | Vref=2.048V; ±3 LSB maximum (text) | 14 |
| Gain error | EG | -3 |  | 3 | LSB | Vref=2.048V | 5 |
| Voltage output range | VO | 0 |  |  | V | RL=10k; max printed as VDD-0.4 V | 6 |
| Output voltage, low-level | VOL(low) |  |  | 0.25 | V | IO(OUT)≤5mA | 6 |
| Output voltage, high-level | VOH(high) | 4.75 |  |  | V | IO(OUT)≤-5mA | 6 |
| Input voltage (REFIN) | VI | 0 |  |  | V | max printed as VDD-2 V | 6 |
| High-level digital input voltage | VIH | 2.4 |  |  | V |  | 6 |
| Low-level digital input voltage | VIL |  |  | 0.8 | V |  | 6 |
| High-level digital input current | IIH | -1 |  | 1 | µA | VI = VDD | 6 |
| Low-level digital input current | IIL | -1 |  | 1 | µA | VI = 0 | 6 |
| Output voltage, low-level (DOUT) | VOL |  |  | 0.4 | V | IO = 2mA | 6 |
| Supply voltage (power supply section) | VDD | 4.5 | 5 | 5.5 | V |  | 6 |
| Power supply current (Vref = 0) | IDD |  | 150 | 250 | µA | VDD=5.5V, no load, all inputs=0V or VDD, Vref=0 | 6 |
| Power supply current (Vref = 2.048V) | IDD |  | 230 | 350 | µA | VDD=5.5V, no load, all inputs=0V or VDD, Vref=2.048V | 6 |
| Setup time, DIN before SCLK high | tsu(DS) | 45 |  |  | ns |  | 6 |
| Hold time, DIN valid after SCLK high | th(DH) | 0 |  |  | ns |  | 6 |
| Setup time, CS low to SCLK high | tsu(CSS) | 1 |  |  | ns |  | 6 |
| Setup time, CS high to SCLK high | tsu(CS1) | 50 |  |  | ns |  | 6 |
| Hold time, SCLK low to CS low | th(CSH0) | 1 |  |  | ns |  | 6 |
| Hold time, SCLK low to CS high | th(CSH1) | 0 |  |  | ns |  | 6 |
| Pulse duration, minimum chip select pulse width high | tw(CS) | 20 |  |  | ns |  | 6 |
| Pulse duration, SCLK low | tw(CL) | 25 |  |  | ns |  | 6 |
| Pulse duration, SCLK high | tw(CH) | 25 |  |  | ns |  | 6 |
| Propagation delay time, DOUT | tpd(DOUT) |  |  | 50 | ns | CL = 50pF | 7 |
| Output slew rate | SR |  | 0.3 | 0.5 | V/µs | CL = 100pF, TA= +25C, RL= 10kΩ | 7 |
| Signal-to-noise + distortion, S/(N+D) | S/(N+D) | 60 |  |  | dB | Vref = 1VPP at 1kHz + 2.048Vdc, code = 11 1111 1111 | 6 |
| Output settling time | ts |  | 12.5 |  | µs | To 0.5LSB, RL = 10kΩ, CL = 100pF | 7 |
| Glitch energy |  |  | 5 |  | nV-s | DIN = All 0s to all 1s | 7 |
| Reference feedthrough |  |  | -80 |  | dB | REFIN = 1VPP at 1kHz + 2.048Vdc | 7 |
| Reference input bandwidth (f-3dB) | f-3dB |  | 30 |  | kHz | REFIN = 0.2VPP + 2.048Vdc | 7 |
| Power-supply rejection ratio, zero scale | PSRR |  | 80 |  | dB | Zero scale | 5 |
| Power-supply rejection ratio, gain | PSRR |  | 80 |  | dB | Gain | 5 |
| Zero-scale-error temperature coefficient |  |  | 3 |  | ppm/C | Vref=2.048V | 5 |
| Gain-error temperature coefficient |  |  | 1 |  | ppm/C | Vref=2.048V | 5 |
| Output load regulation accuracy |  |  | 0.5 |  | LSB | VO(OUT)=2V, RL=2k | 6 |
| Output short circuit current | IOSC |  | 20 |  | mA | OUT to VDD or AGND | 6 |
| Reference input resistance | ri |  | 10 |  | MΩ |  | 6 |
| Reference input capacitance | Ci |  | 5 |  | pF |  | 6 |
| Digital input capacitance | Ci |  | 8 |  | pF |  | 6 |

## CAD (KiCad official)

- Symbol: `HGC5615CM`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `hgc5615cm-etched.step` / `hgc5615cm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hgc5615cm.step` / `hgc5615cm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](docs/hgc5615cm-datasheet.pdf) (19 pp, sha256 `4f15d178132b78e6`, retrieved 2026-11-04, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hgc5615cm-datasheet.pdf)