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HG24LC04M

Public Made by Adom

by adom

HGSEMI EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HG24LC04M

HGSEMI · EEPROM · SOP-8

HG24LC04M from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address input; not used for addressing on the HG24LC04 (no connect, can be connected to ground).
2 A1 input Device address input used for hard-wire addressing on the HG24LC04 (together with A2, up to four 4K devices on one bus).
3 A2 input Device address input used for hard-wire addressing on the HG24LC04 (together with A1, up to four 4K devices on one bus).
4 GND power_in Ground.
5 SDA bidirectional Serial data pin, bidirectional and open-drain, may be wire-ORed with other open-drain or open-collector devices and needs an external pull-up.
6 SCL input Serial clock input; positive edge clocks data into the device and negative edge clocks data out.
7 WP input Write protect; normal read/write when connected to GND, full 4K array protected when connected to VCC.
8 VCC power_in Power supply, 1.7V to 5.5V operating range.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Vcc 1.7 5.5 V 9
Supply Current Icc1 0.4 1 mA Vcc=5.0V; Read @100KHz 9
Supply Current Icc2 2 3 mA Vcc=5.0V; Write @100KHz 9
Standby Current ISB 2 uA Vin=Vcc or GND 9
Input Leakage Current ILI 3 uA Vin=Vcc or GND 9
Output Leakage Current ILO 0.05 3 uA Vout=Vcc or GND 9
Input Low Level VIL -0.6 V 9
Output Low Level VOL3 0.4 V Vcc=5.0V; IOL=3.0mA 9
Output Low Level VOL1 0.2 V Vcc=1.8V; IOL=0.15mA 9
Input/Output Capacitance (SDA) CI/O 8 pF TA = 25℃, f = 1.0 MHz, VI/O = 0V 9
Input Capacitance (A0, A1, A2, SCL) CIN 6 pF TA = 25℃, f = 1.0 MHz, VIN = 0V 9
DC Supply Voltage -0.3 6.5 V 8
Operating Ambient Temperature -40 85 ℃ 8
Storage Temperature -65 150 ℃ 8
Clock Frequency, SCL fSCL 400 KHz 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Frequency, SCL fSCL 1000 KHz 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Pulse Width Low tLOW 1.2 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Pulse Width Low tLOW 0.6 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Pulse Width High tHIGH 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Pulse Width High tHIGH 0.4 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Noise Suppression Time tI 50 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Noise Suppression Time tI 40 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Low to Data Out Valid tAA 0.05 0.9 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Clock Low to Data Out Valid tAA 0.05 0.55 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Time the bus must be free before a new transmission can start tBUF 1.2 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Time the bus must be free before a new transmission can start tBUF 0.5 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Start Hold Time tHD.STA 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Start Hold Time tHD.STA 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Start Setup Time tSU.STA 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Start Setup Time tSU.STA 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Data In Hold Time tHD.DAT 0 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Data In Setup Time tSU.DAT 100 ns 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Inputs Rise Time tR 0.3 us 1.8-volt column; characterized, not 100% tested 9
Inputs Fall Time tF 300 ns 1.8-volt column; characterized, not 100% tested 9
Inputs Fall Time tF 100 ns 5.0-volt column; characterized, not 100% tested 9
Stop Setup Time tSU.STO 0.6 us 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Stop Setup Time tSU.STO 0.25 us 5.0-volt column; CL = 1 TTL Gate and 100 pF 9
Data Out Hold Time tDH 50 ns 1.8-volt column; CL = 1 TTL Gate and 100 pF 9
Write Cycle Time tWR 5 ms 1.8-volt column 9

CAD (KiCad official)

  • Symbol: HG24LC04M
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: hg24lc04m-etched.step / hg24lc04m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hg24lc04m.step / hg24lc04m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (13 pp, sha256 df8e8e0050b9af80, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF