component
HG24C128M
Public Made by Adomby adom
HGSEMI EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownHG24C128M
HGSEMI · EEPROM · SOP-8
HG24C128M from HGSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | E0 | input | Device address input used for hardware addressing (up to 8 devices per bus); if left floating it is internally pulled down to Vss. |
| 2 | E1 | input | Device address input used for hardware addressing (up to 8 devices per bus); if left floating it is internally pulled down to Vss. |
| 3 | E2 | input | Device address input used for hardware addressing (up to 8 devices per bus); if left floating it is internally pulled down to Vss. |
| 4 | Vss | power_in | Ground reference for the VCC supply voltage. |
| 5 | SDA | bidirectional | Bidirectional serial data line, open-drain driven, to be pulled high externally and may be wire-OR'ed with other open-drain or open-collector devices. |
| 6 | SCL | input | Serial clock input; data is clocked in on the positive edge and clocked out on the negative edge of SCL. |
| 7 | WCB | input | Active-low write control: connecting it to VCC inhibits all write operations, connecting it to Vss allows normal writes, and if left floating it is internally pulled down to Vss. |
| 8 | VCC | power_in | Supply voltage, specified from 1.7 V to 5.5 V in the DC characteristics (absolute maximum -0.5 V to 6.5 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | TSTG | -65 | 150 | °C | 5 | ||
| Ambient operating temperature range | TA | -40 | 125 | °C | 5 | ||
| Supply Voltage | VCC | -0.5 | 6.5 | V | 5 | ||
| Input or output range | VIO | -0.5 | 6.5 | V | 5 | ||
| DC output current | IOL | 5 | mA | SDA=0 | 5 | ||
| Lead Temperature (soldering) | TL | 260 | °C | Soldering, 10 seconds | 5 | ||
| Input / Output Capacitance (SDA) | CI/O | 8 | pF | VI/O= Vss | 5 | ||
| Input Capacitance (E0, E1, E2, WCB, SCL) | CIN | 6 | pF | VIN= Vss | 5 | ||
| Supply Voltage (1.7V grade range) | VCC | 1.7 | 5.5 | V | 5 | ||
| Standby Current | Isb | 1 | µA | Vcc = 3.3V, TA = 85°C | 5 | ||
| Standby Current | Isb | 2 | µA | Vcc = 5.5V, TA = 85°C | 5 | ||
| Standby Current | Isb | 3 | µA | Vcc = 5.5V, TA = 105°C | 5 | ||
| Supply Current (read) | ICC1 | 0.2 | 0.4 | mA | Vcc = 5.5V, Read at 400Khz | 5 | |
| Supply Current (write) | ICC2 | 0.8 | 1.6 | mA | Vcc = 5.5V, Write at 400Khz | 5 | |
| Input Leakage Current | ILI | 0.1 | 1 | µA | VIN = VCC or Vss | 5 | |
| Output Leakage Current | ILO | 0.05 | 1 | µA | VOUT = VCC or Vss | 5 | |
| Input Low Level | VIL | -0.5 | V | 5 | |||
| Output Low Level (SDA) | VOL1 | 0.2 | V | VCC = 1.7V (SDA), IOL = 0.15 mA | 5 | ||
| Output Low Level (SDA) | VOL2 | 0.4 | V | VCC = 3.0V (SDA), IOL = 2.1 mA | 5 | ||
| VCC voltage to fall below for ensuring initialization | VPWD | 0.7 | V | 8 | |||
| Minimum duration VCC below VPWD for initialization | tPWD | 300 | us | 8 | |||
| VCC(min.) to device operation | tVSL | 70 | us | 8 | |||
| VCC Rise Time | tVR | 1 | 500000 | us/V | 8 | ||
| Clock Frequency, SCL | fSCL | 400 | kHz | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Clock Frequency, SCL | fSCL | 1000 | kHz | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Clock Pulse Width Low | tLOW | 1.3 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Clock Pulse Width Low | tLOW | 0.4 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Clock Pulse Width High | tHIGH | 0.6 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Clock Pulse Width High | tHIGH | 0.4 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Clock Low to Data Out Valid (min) | tAA | 0.05 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Clock Low to Data Out Valid (max) | tAA | 0.9 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Clock Low to Data Out Valid (max) | tAA | 0.55 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Noise Suppression Time | tI | 0.1 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Noise Suppression Time | tI | 0.05 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Bus free time before new transmission | tBUF | 1.3 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Bus free time before new transmission | tBUF | 0.5 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| START Hold Time | tHD.STA | 0.6 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| START Hold Time | tHD.STA | 0.25 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| START Setup Time | tSU.STA | 0.6 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| START Setup Time | tSU.STA | 0.25 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Data In Hold Time | tHD.DAT | 0 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Data In Setup Time | tSU.DAT | 0.1 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Inputs Rise Time | tR | 0.3 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Inputs Rise Time | tR | 0.1 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Inputs Fall Time | tF | 0.3 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| Inputs Fall Time | tF | 0.1 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| STOP Setup Time | tSU.STO | 0.6 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| STOP Setup Time | tSU.STO | 0.25 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Data Out Hold Time | tDH | 0.05 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| WCB pin Setup Time | tSU.WCB | 1.2 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| WCB pin Setup Time | tSU.WCB | 0.6 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| WCB pin Hold Time | tHD.WCB | 1.2 | µs | 1.7≤VCC≤5.5 (first column group) | 6 | ||
| WCB pin Hold Time | tHD.WCB | 0.6 | µs | 1.7≤VCC≤5.5 (second column group) | 6 | ||
| Write Cycle Time | tWR | 5 | ms | 1.7≤VCC≤5.5 (first column group) | 6 |
CAD (KiCad official)
- Symbol:
HG24C128M - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hg24c128m-etched.step/hg24c128m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hg24c128m.step/hg24c128m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (20 pp, sha256
17783f1cc8fc6b15, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).