component

HG24C02M

Public Made by Adom

by adom

HGSEMI(华冠) EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmemoryhg24c02mfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5h ago
viewers hg24c02m: viewers · Ray 5h ago
hg24c02m-etched.glb Publish 0.1.0 · Ray 5h ago
hg24c02m-etched.step hg24c02m: factory component page (tier=lcsc) · Ray 5h ago
hg24c02m-hero.glb hg24c02m: hero GLB from the etched model (keeps the MPN mark) · Ray 5h ago
hg24c02m-hero.overlay.json Publish 0.1.0 · Ray 5h ago
hg24c02m.glb Publish 0.1.0 · Ray 5h ago
hg24c02m.kicad_mod Publish 0.1.0 · Ray 5h ago
hg24c02m.kicad_sym Publish 0.1.0 · Ray 5h ago
hg24c02m.lbr Publish 0.1.0 · Ray 5h ago
hg24c02m.step Publish 0.1.0 · Ray 5h ago
package.json Publish 0.1.0 · Ray 5h ago
page.json Set visibility: public · Ray 5h ago
README.md Publish 0.1.0 · Ray 5h ago

HG24C02M

HGSEMI(华冠) · EEPROM · SOP-8

HG24C02M from HGSEMI(华冠), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E0 input Device address input that must match the hardwired E0 address bit; if left floating it is internally pulled down to Vss.
2 E1 input Device address input that must match the hardwired E1 address bit; if left floating it is internally pulled down to Vss, allowing up to eight devices on one bus together with E0 and E2.
3 E2 input Device address input that must match the hardwired E2 address bit; if left floating it is internally pulled down to Vss, allowing up to eight devices on one bus.
4 Vss power_in Ground and reference for the VCC supply voltage.
5 SDA bidirectional Open-drain serial data input and output for the I2C-compatible bus, which may be wire-OR'ed with other open-drain or open-collector devices; DC output current (SDA=0) is limited to 5 mA maximum.
6 SCL input Serial clock input that clocks data in on the positive edge and clocks data out on the negative edge.
7 WCB input Active-low write control: connecting WCB to VCC inhibits all write operations to the memory, connecting it to Vss allows normal writes, and it is internally pulled down to Vss if left floating.
8 VCC power_in Supply voltage, specified from 1.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer HGSEMI(华冠)
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage Temperature TSTG -65 150 °C 4
Operating temperature range TA -40 125 °C 4
Supply Voltage (absolute maximum) VCC -0.5 6.5 V 4
Input or output range VIO -0.5 6.5 V 4
DC output current IOL 5 mA SDA=0 4
Lead Temperature TL 260 °C Soldering, 10 seconds 4
Input / Output Capacitance (SDA) CI/O 8 pF VI/O= Vss 4
Input Capacitance (E0, E1, E2, WCB, SCL) CIN 6 pF VIN= Vss 4
Supply Voltage Vcc 1.7 5.5 V 4
Standby Current Isb 1 uA Vcc = 3.3V 4
Standby Current Isb 3 uA Vcc = 5.5V 4
Supply Current (read) ICC1 0.2 0.4 mA Vcc=5.5V, Read at 400khz 4
Supply Current (write) ICC2 0.8 1.6 mA Vcc=5.5V, Write at 400khz 4
Input Leakage Current ILI 0.1 1 µA VIN = VCC or Vss 4
Output Leakage Current ILO 0.05 1 µA VOUT = VCC or Vss 4
Input Low Level VIL -0.5 V 4
Output Low Level (SDA) VOL1 0.2 V VCC = 1.7V (SDA), IOL = 0.15 mA 4
Output Low Level (SDA) VOL2 0.4 V VCC = 3.0V (SDA), IOL = 2.1 mA 4
Clock Frequency, SCL [400 kHz column] fSCL 400 kHz 1.7≤VCC≤5.5 6
Clock Pulse Width Low [400 kHz column] tLOW 1.3 µs 1.7≤VCC≤5.5 6
Clock Pulse Width High [400 kHz column] tHIGH 0.6 µs 1.7≤VCC≤5.5 6
Clock Low to Data Out Valid [400 kHz column] tAA 0.05 0.9 µs 1.7≤VCC≤5.5 6
Noise Suppression Time [400 kHz column] tI 0.1 µs 1.7≤VCC≤5.5 6
Bus free time before new transmission [400 kHz column] tBUF 1.3 µs 1.7≤VCC≤5.5 6
Start Hold Time [400 kHz column] tHD.STA 0.6 µs 1.7≤VCC≤5.5 6
Start Setup Time [400 kHz column] tSU.STA 0.6 µs 1.7≤VCC≤5.5 6
Data In Hold Time [400 kHz column] tHD.DAT 0 µs 1.7≤VCC≤5.5 6
Data In Setup Time [400 kHz column] tSU.DAT 0.1 µs 1.7≤VCC≤5.5 6
Inputs Rise Time [400 kHz column] tR 0.3 µs 1.7≤VCC≤5.5 6
Inputs Fall Time [400 kHz column] tF 0.3 µs 1.7≤VCC≤5.5 6
Stop Setup Time [400 kHz column] tSU.STO 0.6 µs 1.7≤VCC≤5.5 6
Data Out Hold Time [400 kHz column] tDH 0.05 µs 1.7≤VCC≤5.5 6
WCB pin Setup Time [400 kHz column] tSU.WCB 1.2 µs 1.7≤VCC≤5.5 6
WCB pin Hold Time [400 kHz column] tHD.WCB 1.2 µs 1.7≤VCC≤5.5 6
Write Cycle Time [400 kHz column] tWR 5 ms 1.7≤VCC≤5.5 6
Clock Frequency, SCL [1 MHz column] fSCL 1000 kHz 1.7≤VCC≤5.5 6
Clock Pulse Width Low [1 MHz column] tLOW 0.4 µs 1.7≤VCC≤5.5 6
Clock Pulse Width High [1 MHz column] tHIGH 0.4 µs 1.7≤VCC≤5.5 6
Clock Low to Data Out Valid [1 MHz column] tAA 0.05 0.55 µs 1.7≤VCC≤5.5 6
Noise Suppression Time [1 MHz column] tI 0.05 µs 1.7≤VCC≤5.5 6
Bus free time before new transmission [1 MHz column] tBUF 0.5 µs 1.7≤VCC≤5.5 6
Start Hold Time [1 MHz column] tHD.STA 0.25 µs 1.7≤VCC≤5.5 6
Start Setup Time [1 MHz column] tSU.STA 0.25 µs 1.7≤VCC≤5.5 6
Data In Hold Time [1 MHz column] tHD.DAT 0 µs 1.7≤VCC≤5.5 6
Data In Setup Time [1 MHz column] tSU.DAT 0.1 µs 1.7≤VCC≤5.5 6
Inputs Rise Time [1 MHz column] tR 0.3 µs 1.7≤VCC≤5.5 6
Inputs Fall Time [1 MHz column] tF 0.1 µs 1.7≤VCC≤5.5 6
Stop Setup Time [1 MHz column] tSU.STO 0.25 µs 1.7≤VCC≤5.5 6
Data Out Hold Time [1 MHz column] tDH 0.05 µs 1.7≤VCC≤5.5 6
WCB pin Setup Time [1 MHz column] tSU.WCB 0.6 µs 1.7≤VCC≤5.5 6
WCB pin Hold Time [1 MHz column] tHD.WCB 0.6 µs 1.7≤VCC≤5.5 6
Write Cycle Time [1 MHz column] tWR 5 ms 1.7≤VCC≤5.5 6
VCC voltage needed to go below VPWD for ensuring initialization VPWD 0.7 V 8
Minimum duration for ensuring initialization occurs tPWD 300 us 8
VCC(min.) to device operation tVSL 70 us 8
VCC Rise Time tVR 1 500000 us/V 8

CAD (KiCad official)

  • Symbol: HG24C02M
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: hg24c02m-etched.step / hg24c02m-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hg24c02m.step / hg24c02m.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI(华冠) datasheet (18 pp, sha256 ac9e22c1abbbd678, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF