# HESDSLC5V0T2-TP

**HXY MOSFET** · ESD And Surge Protection (TVS/ESD) · SOT-23

HESDSLC5V0T2-TP from HXY MOSFET, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | Protected unidirectional line 1 (transil diode to common pin 3), 5 V working voltage, ±15 kV air / ±8 kV contact IEC61000-4-2. |
| 2 | I/O2 | passive | Protected unidirectional line 2 (transil diode to common pin 3), 5 V working voltage, ±15 kV air / ±8 kV contact IEC61000-4-2. |
| 3 | COMMON | passive | Common node joining both transil diodes in the circuit diagram; the datasheet does not label it as GND or give its connection. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HXY MOSFET |
| Package | SOT-23 |
| Category | Circuit Protection |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Peak Pulse Power | PPP |  |  | 100 |  | tp = 8/20μs | 1 |
| Maximum lead temperature for soldering | TL |  |  | 260 | °C | during 10s | 1 |
| Storage Temperature Range | Tstg | -55 |  | 150 | °C |  | 1 |
| Operating Temperature Range | Top | -40 |  | 125 | °C |  | 1 |
| Maximum junction temperature | Tj |  |  | 150 | °C |  | 1 |
| ESD immunity, air discharge | IEC61000-4-2 (ESD) | -15 |  | 15 | KV | air discharge | 1 |
| ESD immunity, contact discharge | IEC61000-4-2 (ESD) | -8 |  | 8 | KV | contact discharge | 1 |
| Breakdown voltage | VBR | 6 |  |  | V | pulse test current IT, ambient 25℃ (Note 1) | 2 |
| Reverse leakage current | IR |  |  | 0.5 | uA | @ VRWM | 2 |

## CAD (KiCad official)

- Symbol: `HESDSLC5V0T2-TP`
- Footprint: `Package_TO_SOT_SMD:SOT-23`
- 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files: `hesdslc5v0t2-tp-etched.step` / `hesdslc5v0t2-tp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hesdslc5v0t2-tp.step` / `hesdslc5v0t2-tp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HXY MOSFET datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603009268605853696) (4 pp, sha256 `308c5c02e548642c`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hesdslc5v0t2-tp-datasheet.pdf)