# HEF4104BT

**Nexperia** · Translators, Level Shifters · SOIC-16

HEF4104BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD(B) | power_in | Supply voltage for port B; must be greater than or equal to VDD(A), with 15 V as the recommended maximum and -0.5 V to +18 V as the absolute limit. |
| 2 | ~B0 | tri_state | Complementary data output B0, the inverse of data output B0; it goes to high-impedance OFF-state when OE is LOW. |
| 3 | B0 | tri_state | Data output B0 follows data input A0 when OE is HIGH and goes to high-impedance OFF-state when OE is LOW. |
| 4 | A0 | input | Data input A0 on the port A supply domain, with an input range of 0 V to VDD(A) and clamp diodes that allow a current-limited external resistor for voltages above VDD(A). |
| 5 | A1 | input | Data input A1 on the port A supply domain, with an input range of 0 V to VDD(A) and clamp diodes that allow a current-limited external resistor for voltages above VDD(A). |
| 6 | B1 | tri_state | Data output B1 follows data input A1 when OE is HIGH and goes to high-impedance OFF-state when OE is LOW. |
| 7 | ~B1 | tri_state | Complementary data output B1, the inverse of data output B1; it goes to high-impedance OFF-state when OE is LOW. |
| 8 | VSS | power_in | Common negative supply voltage, 0 V (ground) reference for all voltages in the device. |
| 9 | ~B2 | tri_state | Complementary data output B2, the inverse of data output B2; it goes to high-impedance OFF-state when OE is LOW. |
| 10 | B2 | tri_state | Data output B2 follows data input A2 when OE is HIGH and goes to high-impedance OFF-state when OE is LOW. |
| 11 | A2 | input | Data input A2 on the port A supply domain, with an input range of 0 V to VDD(A) and clamp diodes that allow a current-limited external resistor for voltages above VDD(A). |
| 12 | A3 | input | Data input A3 on the port A supply domain, with an input range of 0 V to VDD(A) and clamp diodes that allow a current-limited external resistor for voltages above VDD(A). |
| 13 | B3 | tri_state | Data output B3 follows data input A3 when OE is HIGH and goes to high-impedance OFF-state when OE is LOW. |
| 14 | ~B3 | tri_state | Complementary data output B3, the inverse of data output B3; it goes to high-impedance OFF-state when OE is LOW. |
| 15 | OE | input | Output enable input; HIGH passes the An inputs to the outputs, while LOW forces all Bn and Bn outputs into the high-impedance OFF-state. |
| 16 | VDD(A) | power_in | Supply voltage for port A; must be at least 3 V and less than or equal to VDD(B), with -0.5 V to +18 V as the absolute limit. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage A | VDD(A) | -0.5 |  | 18 | V | port A; VDD(A) ≤ VDD(B) | 3 |
| supply voltage B | VDD(B) | -0.5 |  | 18 | V | port B; VDD(B) ≥ VDD(A) | 3 |
| input clamping current | IIK | -10 |  | 10 | mA | VI < -0.5 V or VI > VDD(A) + 0.5 V | 3 |
| input voltage | VI | -0.5 |  |  | V |  | 3 |
| output clamping current | IOK | -10 |  | 10 | mA | VO < -0.5 V or VO > VDD(B) + 0.5 V | 3 |
| input/output current | II/O | -10 |  | 10 | mA |  | 3 |
| supply current | IDD |  |  | 50 | mA |  | 3 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 3 |
| ambient temperature | Tamb | -40 |  | 85 | °C |  | 3 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +85 °C | 3 |
| power dissipation per output | P |  |  | 100 | mW |  | 3 |
| supply voltage A | VDD(A) | 3 |  |  | V |  | 4 |
| supply voltage B | VDD(B) |  |  | 15 | V | VDD(B) ≥ VDD(A) | 4 |
| input voltage | VI | 0 |  |  | V |  | 4 |
| ambient temperature | Tamb | -40 |  | 85 | °C | in free air | 4 |
| input transition rise and fall rate | Δt/ΔV |  |  | 3.75 | μs/V | VDD(A) = 5 V | 4 |
| input transition rise and fall rate | Δt/ΔV |  |  | 0.5 | μs/V | VDD(A) = 10 V | 4 |
| input transition rise and fall rate | Δt/ΔV |  |  | 0.08 | μs/V | VDD(A) = 15 V | 4 |
| HIGH-level input voltage | VIH | 3.5 |  |  | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C | 4 |
| HIGH-level input voltage | VIH | 7 |  |  | V | /IO/ < 1 μA; VDD = 10 V; Tamb = -40 °C | 4 |
| HIGH-level input voltage | VIH | 11 |  |  | V | /IO/ < 1 μA; VDD = 15 V; Tamb = -40 °C | 4 |
| LOW-level input voltage | VIL |  |  | 1.5 | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C | 4 |
| LOW-level input voltage | VIL |  |  | 3 | V | /IO/ < 1 μA; VDD = 10 V; Tamb = -40 °C | 4 |
| LOW-level input voltage | VIL |  |  | 4 | V | /IO/ < 1 μA; VDD = 15 V; Tamb = -40 °C | 4 |
| HIGH-level output voltage | VOH | 4.95 |  |  | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C | 4 |
| HIGH-level output voltage | VOH | 9.95 |  |  | V | /IO/ < 1 μA; VDD = 10 V; Tamb = -40 °C | 4 |
| HIGH-level output voltage | VOH | 14.95 |  |  | V | /IO/ < 1 μA; VDD = 15 V; Tamb = -40 °C | 4 |
| LOW-level output voltage | VOL |  |  | 0.05 | V | /IO/ < 1 μA; VDD = 5 V; Tamb = -40 °C | 4 |
| supply current | IDD |  |  | 150 | μA | all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = +85 °C | 4 |
| supply current | IDD |  |  | 300 | μA | all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = +85 °C | 4 |
| supply current | IDD |  |  | 600 | μA | all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = +85 °C | 4 |
| OFF-state output current HIGH | IOZ |  |  | 12 | μA | VO = VDD(B); VDD = 15 V; Tamb = +85 °C | 4 |
| OFF-state output current LOW | IOZ |  |  | -12 | μA | VO = VSS; VDD = 15 V; Tamb = +85 °C | 4 |
| input capacitance | CI |  |  | 7.5 | pF | digital inputs; Tamb = +85 °C | 5 |
| HIGH to LOW propagation delay | tPHL |  |  | 340 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 5 |
| HIGH to LOW propagation delay | tPHL |  |  | 160 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 5 |
| HIGH to LOW propagation delay | tPHL |  |  | 135 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 5 |
| LOW to HIGH propagation delay | tPLH |  |  | 340 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 5 |
| LOW to HIGH propagation delay | tPLH |  |  | 160 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 5 |
| LOW to HIGH propagation delay | tPLH |  |  | 140 | ns | An to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 5 |
| HIGH to LOW output transition time | tTHL |  |  | 120 | ns | Bn or Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 5 |
| HIGH to LOW output transition time | tTHL |  |  | 60 | ns | Bn or Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 5 |
| HIGH to LOW output transition time | tTHL |  |  | 40 | ns | Bn or Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 5 |
| LOW to HIGH output transition time | tTLH |  |  | 120 | ns | Bn or Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 5 |
| LOW to HIGH output transition time | tTLH |  |  | 60 | ns | Bn or Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 5 |
| LOW to HIGH output transition time | tTLH |  |  | 40 | ns | Bn or Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 5 |
| HIGH to OFF-state propagation delay | tPHZ |  |  | 135 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 6 |
| HIGH to OFF-state propagation delay | tPHZ |  |  | 110 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 6 |
| HIGH to OFF-state propagation delay | tPHZ |  |  | 120 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 6 |
| LOW to OFF-state propagation delay | tPLZ |  |  | 135 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 6 |
| LOW to OFF-state propagation delay | tPLZ |  |  | 105 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 6 |
| LOW to OFF-state propagation delay | tPLZ |  |  | 110 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 6 |
| OFF-state to HIGH propagation delay | tPZH |  |  | 395 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 6 |
| OFF-state to HIGH propagation delay | tPZH |  |  | 195 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 6 |
| OFF-state to HIGH propagation delay | tPZH |  |  | 165 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 6 |
| OFF-state to LOW propagation delay | tPZL |  |  | 395 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 5 V; Tamb = 25 °C | 6 |
| OFF-state to LOW propagation delay | tPZL |  |  | 190 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 10 V; Tamb = 25 °C | 6 |
| OFF-state to LOW propagation delay | tPZL |  |  | 160 | ns | OE to Bn, Bn; VDD(A) = VDD(B) = 15 V; Tamb = 25 °C | 6 |

## CAD (KiCad official)

- Symbol: `HEF4104BT`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `hef4104bt-etched.step` / `hef4104bt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hef4104bt.step` / `hef4104bt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586193698200043520) (12 pp, sha256 `7e651ba2e78481da`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hef4104bt-datasheet.pdf)