component
HEF4093BT-JSM
Public Made by Adomby adom
JSMSEMI Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHEF4093BT-JSM
JSMSEMI · Logic Gates · SOP-14
HEF4093BT-JSM from JSMSEMI, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Schmitt-trigger input A of NAND gate 1 (output J), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 2 | B | input | Schmitt-trigger input B of NAND gate 1 (output J), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 3 | J | output | Output of NAND gate 1, J = NOT(A AND B). |
| 4 | K | output | Output of NAND gate 2, K = NOT(C AND D). |
| 5 | C | input | Schmitt-trigger input C of NAND gate 2 (output K), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 6 | D | input | Schmitt-trigger input D of NAND gate 2 (output K), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 7 | VSS | power_in | Ground / negative supply pin. |
| 8 | E | input | Schmitt-trigger input E of NAND gate 3 (output L), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 9 | F | input | Schmitt-trigger input F of NAND gate 3 (output L), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 10 | L | output | Output of NAND gate 3, L = NOT(E AND F). |
| 11 | M | output | Output of NAND gate 4, M = NOT(G AND H). |
| 12 | G | input | Schmitt-trigger input G of NAND gate 4 (output M), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 13 | H | input | Schmitt-trigger input H of NAND gate 4 (output M), logic levels within VSS-0.5 V to VDD+0.5 V. |
| 14 | VDD | power_in | Positive supply pin, 3.0 V to 18 V operating range, absolute maximum -0.5 to 20 V (recommended 3 V to 15 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | JSMSEMI |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
HEF4093BT-JSM - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
hef4093bt-jsm-etched.step/hef4093bt-jsm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hef4093bt-jsm.step/hef4093bt-jsm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: JSMSEMI datasheet (5 pp, sha256
ee3375470c90bace, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).