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HEF4071BT

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Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HEF4071BT

Nexperia · Logic Gates · SOIC-14

HEF4071BT from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input A of gate 1 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
2 1B input Input B of gate 1 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
3 1Y output Output of gate 1, implementing Y = A OR B (HIGH when either input is HIGH, LOW only when both inputs are LOW).
4 2Y output Output of gate 2, implementing Y = A OR B (HIGH when either input is HIGH, LOW only when both inputs are LOW).
5 2A input Input A of gate 2 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
6 2B input Input B of gate 2 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
7 VSS power_in Ground reference, 0 V.
8 3A input Input A of gate 3 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
9 3B input Input B of gate 3 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
10 3Y output Output of gate 3, implementing Y = A OR B (HIGH when either input is HIGH, LOW only when both inputs are LOW).
11 4Y output Output of gate 4, implementing Y = A OR B (HIGH when either input is HIGH, LOW only when both inputs are LOW).
12 4A input Input A of gate 4 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
13 4B input Input B of gate 4 (quad 2-input OR); includes a clamp diode, and the input voltage range is 0 V to VDD, with current-limiting resistors usable to interface voltages above VDD.
14 VDD power_in Supply voltage; recommended operating range 3 V to 15 V, absolute maximum 18 V (referenced to VSS).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage (absolute maximum ratings) VDD -0.5 18 V 3
input clamping current IIK -10 10 mA VI < -0.5 V or VI > VDD + 0.5 V 3
input voltage VI -0.5 V max printed as VDD + 0.5 V 3
output clamping current IOK -10 10 mA VO < -0.5 V or VO > VDD + 0.5 V 3
input/output current II/O -10 10 mA 3
supply current IDD 50 mA 3
storage temperature Tstg -65 150 °C 3
ambient temperature Tamb -40 125 °C 3
total power dissipation Ptot 500 mW Tamb = -40 °C to + 125 °C 3
power dissipation per output P 100 mW 3
supply voltage (recommended) VDD 3 15 V 3
input voltage (recommended) VI 0 V max printed as VDD 3
ambient temperature in free air (recommended) Tamb -40 125 °C 3
input transition rise and fall rate Δt/ΔV 3.75 μs/V VDD = 5 V 3
input transition rise and fall rate Δt/ΔV 0.5 μs/V VDD = 10 V 3
input transition rise and fall rate Δt/ΔV 0.08 μs/V VDD = 15 V 3
HIGH-level input voltage VIH 3.5 V /IO/ < 1 μA; VDD = 5 V; same value in all Tamb columns (-40 °C to +125 °C) 3
HIGH-level input voltage VIH 7 V /IO/ < 1 μA; VDD = 10 V; same value in all Tamb columns (-40 °C to +125 °C) 3
HIGH-level input voltage VIH 11 V /IO/ < 1 μA; VDD = 15 V; same value in all Tamb columns (-40 °C to +125 °C) 3
LOW-level input voltage VIL 1.5 V /IO/ < 1 μA; VDD = 5 V; same value in all Tamb columns (-40 °C to +125 °C) 3
LOW-level input voltage VIL 3 V /IO/ < 1 μA; VDD = 10 V; same value in all Tamb columns (-40 °C to +125 °C) 3
LOW-level input voltage VIL 4 V /IO/ < 1 μA; VDD = 15 V; same value in all Tamb columns (-40 °C to +125 °C) 3
HIGH-level output voltage VOH 4.95 V /IO/ < 1 μA; VDD = 5 V; same value in all Tamb columns (-40 °C to +125 °C) 3
HIGH-level output voltage VOH 9.95 V /IO/ < 1 μA; VDD = 10 V; same value in all Tamb columns (-40 °C to +125 °C) 3
HIGH-level output voltage VOH 14.95 V /IO/ < 1 μA; VDD = 15 V; same value in all Tamb columns (-40 °C to +125 °C) 3
LOW-level output voltage VOL 0.05 V /IO/ < 1 μA; VDD = 5 V; same value in all Tamb columns (-40 °C to +125 °C) 4
input capacitance CI 7.5 pF 4
HIGH to LOW propagation delay (nA or nB to nY) tPHL 55 115 ns Tamb = 25 °C; VDD = 5 V 4
HIGH to LOW propagation delay (nA or nB to nY) tPHL 25 50 ns Tamb = 25 °C; VDD = 10 V 4
HIGH to LOW propagation delay (nA or nB to nY) tPHL 20 35 ns Tamb = 25 °C; VDD = 15 V 4
LOW to HIGH propagation delay (nA or nB to nY) tPLH 45 90 ns Tamb = 25 °C; VDD = 5 V 4
LOW to HIGH propagation delay (nA or nB to nY) tPLH 20 45 ns Tamb = 25 °C; VDD = 10 V 4
LOW to HIGH propagation delay (nA or nB to nY) tPLH 15 30 ns Tamb = 25 °C; VDD = 15 V 4
transition time tt 60 120 ns Tamb = 25 °C; VDD = 5 V 4
transition time tt 30 60 ns Tamb = 25 °C; VDD = 10 V 4
transition time tt 20 40 ns Tamb = 25 °C; VDD = 15 V 4
supply current IDD 0.25 μA all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = -40 °C 4
supply current IDD 7.5 μA all valid input combinations; IO = 0 A; VDD = 5 V; Tamb = +125 °C 4
supply current IDD 0.5 μA all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = -40 °C 4
supply current IDD 15 μA all valid input combinations; IO = 0 A; VDD = 10 V; Tamb = +125 °C 4
supply current IDD 1 μA all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = -40 °C 4
supply current IDD 30 μA all valid input combinations; IO = 0 A; VDD = 15 V; Tamb = +125 °C 4
HIGH-level output current IOH -1.7 mA VO = 2.5 V; VDD = 5 V; Tamb = -40 °C 4
HIGH-level output current IOH -1.1 mA VO = 2.5 V; VDD = 5 V; Tamb = +125 °C 4
HIGH-level output current IOH -0.64 mA VO = 4.6 V; VDD = 5 V; Tamb = -40 °C 4
HIGH-level output current IOH -0.36 mA VO = 4.6 V; VDD = 5 V; Tamb = +125 °C 4
HIGH-level output current IOH -1.6 mA VO = 9.5 V; VDD = 10 V; Tamb = -40 °C 4
HIGH-level output current IOH -0.9 mA VO = 9.5 V; VDD = 10 V; Tamb = +125 °C 4
HIGH-level output current IOH -4.2 mA VO = 13.5 V; VDD = 15 V; Tamb = -40 °C 4
HIGH-level output current IOH -2.4 mA VO = 13.5 V; VDD = 15 V; Tamb = +125 °C 4
LOW-level output current IOL 0.64 mA VO = 0.4 V; VDD = 5 V; Tamb = -40 °C 4
LOW-level output current IOL 0.36 mA VO = 0.4 V; VDD = 5 V; Tamb = +125 °C 4
LOW-level output current IOL 1.6 mA VO = 0.5 V; VDD = 10 V; Tamb = -40 °C 4
LOW-level output current IOL 0.9 mA VO = 0.5 V; VDD = 10 V; Tamb = +125 °C 4
LOW-level output current IOL 4.2 mA VO = 1.5 V; VDD = 15 V; Tamb = -40 °C 4
LOW-level output current IOL 2.4 mA VO = 1.5 V; VDD = 15 V; Tamb = +125 °C 4
input leakage current II -0.1 0.1 μA VDD = 15 V; Tamb = -40 °C 4
input leakage current II -1 1 μA VDD = 15 V; Tamb = +125 °C 4

CAD (KiCad official)

  • Symbol: HEF4071BT
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: hef4071bt-etched.step / hef4071bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4071bt.step / hef4071bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (9 pp, sha256 3b3a941dbd201c9a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF