HEF4060BT

@@ -0,0 +1,56 @@+# HEF4060BT++**Nexperia** · Counters / Dividers · SOIC-16++HEF4060BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q11 | output | Buffered counter output for the 11th ripple-carry stage. CMOS push-pull output; VOH >= VDD-0.05 V at |IO| < 1 uA. |+| 2 | Q12 | output | Buffered counter output for the 12th ripple-carry stage. CMOS push-pull output. |+| 3 | Q13 | output | Buffered counter output for the 13th ripple-carry stage. CMOS push-pull output. |+| 4 | Q5 | output | Buffered counter output for the 5th ripple-carry stage. CMOS push-pull output. |+| 5 | Q4 | output | Buffered counter output for the 4th ripple-carry stage. CMOS push-pull output. |+| 6 | Q6 | output | Buffered counter output for the 6th ripple-carry stage. CMOS push-pull output. |+| 7 | Q3 | output | Buffered counter output for the 3rd ripple-carry stage. CMOS push-pull output. |+| 8 | VSS | power_in | Ground supply voltage (0 V reference). |+| 9 | CEXT | passive | External capacitor connection for the on-chip RC/crystal oscillator. Leave floating when driving RS with an external clock. |+| 10 | REXT | passive | Oscillator pin; external resistor connection for the on-chip RC/crystal oscillator. Leave floating when driving RS with an external clock. |+| 11 | RS | input | Clock input / oscillator pin. Counter advances on HIGH-to-LOW transition of RS. May be driven by an external clock signal in lieu of using the internal oscillator. |+| 12 | MR | input | Master reset (asynchronous, active HIGH). A HIGH level clears all counter stages and forces all outputs LOW independent of other inputs. |+| 13 | Q8 | output | Buffered counter output for the 8th ripple-carry stage. CMOS push-pull output. |+| 14 | Q7 | output | Buffered counter output for the 7th ripple-carry stage. CMOS push-pull output. |+| 15 | Q9 | output | Buffered counter output for the 9th ripple-carry stage. CMOS push-pull output. |+| 16 | VDD | power_in | Positive supply voltage. Operating range 3.0 V to 15.0 V (absolute max +18 V). Bypass close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `HEF4060BT`+- `HEF4060BTT`++## CAD (KiCad official)++- Symbol: `HEF4060BT`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/HEF4060BT.pdf) (14 pp, sha256 `3cbb319a05862869`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/hef4060bt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "hef4060bt",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Counters / Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "hef4060bt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "hef4060bt.kicad_sym",+    "hef4060bt.kicad_mod",+    "hef4060bt.glb",+    "hef4060bt.step",+    "hef4060bt.lbr",+    "docs/hero.png",+    "docs/hef4060bt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file