# HEF4052BT

**Nexperia** · Analog Switches, Multiplexers · SOIC-16

HEF4052BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 2Y0 | bidirectional | Independent input/output of switch 2 (channel 2Y0), routed to common terminal 2Z when E is LOW and S1, S2 select channel 0. |
| 2 | 2Y2 | bidirectional | Independent input/output of switch 2 (channel 2Y2), routed to common terminal 2Z when E is LOW and the select code selects channel 2. |
| 3 | 2Z | bidirectional | Common output or input of switch 2, connected to one of 2Y0 to 2Y3 under control of S1, S2 and E. |
| 4 | 2Y3 | bidirectional | Independent input/output of switch 2 (channel 2Y3), routed to common terminal 2Z when E is LOW and the select code selects channel 3. |
| 5 | 2Y1 | bidirectional | Independent input/output of switch 2 (channel 2Y1), routed to common terminal 2Z when E is LOW and the select code selects channel 1. |
| 6 | E | input | Enable input, active LOW; when HIGH, all switches are turned off regardless of S1 and S2. |
| 7 | VEE | power_in | Supply voltage for the analog switch channels; limiting value is -18 V to +0.5 V referenced to VDD. |
| 8 | VSS | power_in | Ground supply voltage; the datasheet references all voltages to VSS = 0 V. |
| 9 | S2 | input | Digital select input; together with S1 it selects which of the four channels (nY0 to nY3) connects to nZ. |
| 10 | S1 | input | Digital select input; together with S2 it selects which of the four channels (nY0 to nY3) connects to nZ. |
| 11 | 1Y3 | bidirectional | Independent input/output of switch 1 (channel 1Y3), routed to common terminal 1Z when E is LOW and the select code selects channel 3. |
| 12 | 1Y0 | bidirectional | Independent input/output of switch 1 (channel 1Y0), routed to common terminal 1Z when E is LOW and S1, S2 select channel 0. |
| 13 | 1Z | bidirectional | Common output or input of switch 1, connected to one of 1Y0 to 1Y3 under control of S1, S2 and E. |
| 14 | 1Y1 | bidirectional | Independent input/output of switch 1 (channel 1Y1), routed to common terminal 1Z when E is LOW and the select code selects channel 1. |
| 15 | 1Y2 | bidirectional | Independent input/output of switch 1 (channel 1Y2), routed to common terminal 1Z when E is LOW and the select code selects channel 2. |
| 16 | VDD | power_in | Positive supply voltage; recommended operating range is 3 V to 15 V, with an absolute maximum of -0.5 V to +18 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Interface |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD (recommended) | VDD | 3 |  | 15 | V | see Fig. 8 | 6 |
| Input voltage VI (recommended) | VI | 0 |  |  | V |  | 6 |
| Ambient temperature Tamb (recommended) | Tamb | -40 |  | 125 | °C | in free air | 6 |
| Input transition rise and fall rate | Δt/ΔV |  |  | 3.75 | μs/V | VDD = 5 V | 6 |
| Input transition rise and fall rate | Δt/ΔV |  |  | 0.5 | μs/V | VDD = 10 V | 6 |
| Input transition rise and fall rate | Δt/ΔV |  |  | 0.08 | μs/V | VDD = 15 V | 6 |
| Supply voltage VDD (absolute maximum) | VDD | -0.5 |  | 18 | V |  | 6 |
| Supply voltage VEE (absolute maximum) | VEE | -18 |  | 0.5 | V | referenced to VDD | 6 |
| Input clamping current IIK | IIK | -10 |  | 10 | mA | pins Sn and E; VI < -0.5 V, or VI > VDD + 0.5 V | 6 |
| Input voltage VI (absolute maximum) | VI | -0.5 |  |  | V |  | 6 |
| Input/output current II/O | II/O | -10 |  | 10 | mA |  | 6 |
| Supply current IDD (absolute maximum) | IDD |  |  | 50 | mA |  | 6 |
| Storage temperature Tstg | Tstg | -65 |  | 150 | °C |  | 6 |
| Ambient temperature Tamb (absolute maximum) | Tamb | -40 |  | 125 | °C |  | 6 |
| Total power dissipation Ptot | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 6 |
| Power dissipation per output P | P |  |  | 100 | mW |  | 6 |
| HIGH-level input voltage VIH | VIH | 3.5 |  |  | V | VDD = 5 V; /IO/ < 1 μA | 7 |
| HIGH-level input voltage VIH | VIH | 7 |  |  | V | VDD = 10 V; /IO/ < 1 μA | 7 |
| HIGH-level input voltage VIH | VIH | 11 |  |  | V | VDD = 15 V; /IO/ < 1 μA | 7 |
| LOW-level input voltage VIL | VIL |  |  | 1.5 | V | VDD = 5 V; /IO/ < 1 μA | 7 |
| LOW-level input voltage VIL | VIL |  |  | 3 | V | VDD = 10 V; /IO/ < 1 μA | 7 |
| LOW-level input voltage VIL | VIL |  |  | 4 | V | VDD = 15 V; /IO/ < 1 μA | 7 |
| Input leakage current II | II | -0.1 |  | 0.1 | μA | VDD = 15 V; Tamb = -40 °C | 7 |
| Input leakage current II | II | -1 |  | 1 | μA | VDD = 15 V; Tamb = +125 °C | 7 |
| OFF-state leakage current IS(OFF) Z port | IS(OFF) |  |  | 1000 | nA | Z port; all channels OFF; see Fig. 9; VDD = 15 V; Tamb = +25 °C | 7 |
| OFF-state leakage current IS(OFF) Y port | IS(OFF) |  |  | 200 | nA | Y port; per channel; see Fig. 10; VDD = 15 V; Tamb = +25 °C | 7 |
| Supply current IDD | IDD |  |  | 5 | μA | IO = 0 A; VDD = 5 V; Tamb = -40 °C | 7 |
| Supply current IDD | IDD |  |  | 150 | μA | IO = 0 A; VDD = 5 V; Tamb = +125 °C | 7 |
| Supply current IDD | IDD |  |  | 10 | μA | IO = 0 A; VDD = 10 V; Tamb = -40 °C | 7 |
| Supply current IDD | IDD |  |  | 300 | μA | IO = 0 A; VDD = 10 V; Tamb = +125 °C | 7 |
| Supply current IDD | IDD |  |  | 20 | μA | IO = 0 A; VDD = 15 V; Tamb = -40 °C | 7 |
| Supply current IDD | IDD |  |  | 600 | μA | IO = 0 A; VDD = 15 V; Tamb = +125 °C | 7 |
| Input capacitance CI | CI |  |  | 7.5 | pF | Sn, E inputs | 7 |
| ON resistance (peak) RON(peak) | RON(peak) |  | 350 | 2500 | Ω | VI = 0 V to VDD - VEE; VDD - VEE = 5 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (peak) RON(peak) | RON(peak) |  | 80 | 245 | Ω | VI = 0 V to VDD - VEE; VDD - VEE = 10 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (peak) RON(peak) | RON(peak) |  | 60 | 175 | Ω | VI = 0 V to VDD - VEE; VDD - VEE = 15 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (VI = 0 V) |  |  | 115 | 340 | Ω | VI = 0 V; VDD - VEE = 5 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (VI = 0 V) |  |  | 50 | 160 | Ω | VI = 0 V; VDD - VEE = 10 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (VI = 0 V) |  |  | 40 | 115 | Ω | VI = 0 V; VDD - VEE = 15 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (rail) RON(rail) | RON(rail) |  | 120 | 365 | Ω | VI = VDD - VEE; VDD - VEE = 5 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (rail) RON(rail) | RON(rail) |  | 65 | 200 | Ω | VI = VDD - VEE; VDD - VEE = 10 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| ON resistance (rail) RON(rail) | RON(rail) |  | 50 | 155 | Ω | VI = VDD - VEE; VDD - VEE = 15 V; Tamb = 25 °C; ISW = 200 μA; see Fig. 11 and Fig. 12 | 8 |
| HIGH to LOW propagation delay tPHL (Sn to nYn, nZ) | tPHL |  | 150 | 305 | ns | Sn to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 14 | 9 |
| HIGH to LOW propagation delay tPHL (Sn to nYn, nZ) | tPHL |  | 65 | 135 | ns | Sn to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 14 | 9 |
| HIGH to LOW propagation delay tPHL (Sn to nYn, nZ) | tPHL |  | 50 | 100 | ns | Sn to nYn, nZ; VDD = 15 V; Tamb = 25 °C; see Fig. 14 | 9 |
| LOW to HIGH propagation delay tPLH (Sn to nYn, nZ) | tPLH |  | 150 | 300 | ns | Sn to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 14 | 9 |
| LOW to HIGH propagation delay tPLH (Sn to nYn, nZ) | tPLH |  | 75 | 150 | ns | Sn to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 14 | 9 |
| LOW to HIGH propagation delay tPLH (Sn to nYn, nZ) | tPLH |  | 50 | 100 | ns | Sn to nYn, nZ; VDD = 15 V; Tamb = 25 °C; see Fig. 14 | 9 |
| HIGH to OFF-state propagation delay tPHZ (E to nYn, nZ) | tPHZ |  | 95 | 190 | ns | E to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 15 | 9 |
| HIGH to OFF-state propagation delay tPHZ (E to nYn, nZ) | tPHZ |  | 90 | 180 | ns | E to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 15 | 9 |
| HIGH to OFF-state propagation delay tPHZ (E to nYn, nZ) | tPHZ |  | 85 | 180 | ns | E to nYn, nZ; VDD = 15 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to HIGH propagation delay tPZH (E to nYn, nZ) | tPZH |  | 130 | 260 | ns | E to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to HIGH propagation delay tPZH (E to nYn, nZ) | tPZH |  | 55 | 115 | ns | E to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to HIGH propagation delay tPZH (E to nYn, nZ) | tPZH |  | 45 | 85 | ns | E to nYn, nZ; VDD = 15 V; Tamb = 25 °C; see Fig. 15 | 9 |
| LOW to OFF-state propagation delay tPLZ (E to nYn, nZ) | tPLZ |  | 100 | 205 | ns | E to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 15 | 9 |
| LOW to OFF-state propagation delay tPLZ (E to nYn, nZ) | tPLZ |  | 90 | 180 | ns | E to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to LOW propagation delay tPZL (E to nYn, nZ) | tPZL |  | 120 | 240 | ns | E to nYn, nZ; VDD = 5 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to LOW propagation delay tPZL (E to nYn, nZ) | tPZL |  | 50 | 100 | ns | E to nYn, nZ; VDD = 10 V; Tamb = 25 °C; see Fig. 15 | 9 |
| OFF-state to LOW propagation delay tPZL (E to nYn, nZ) | tPZL |  | 35 | 75 | ns | E to nYn, nZ; VDD = 15 V; Tamb = 25 °C; see Fig. 15 | 9 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | IIK input clamping current pins Sn and E; VI < -0.5 V, or VI | 6 |

## CAD (KiCad official)

- Symbol: `HEF4052BT`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `hef4052bt-etched.step` / `hef4052bt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `hef4052bt.step` / `hef4052bt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172926697066496) (18 pp, sha256 `5ab031dfd60a59f0`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/hef4052bt-datasheet.pdf)