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HEF4051BTT

Public Made by Adom

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Nexperia Signal Switches, Multiplexers, Decoders, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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HEF4051BTT

Nexperia · Signal Switches, Multiplexers, Decoders · TSSOP-16

HEF4051BTT from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y4 bidirectional Independent analog input/output channel 4 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
2 Y6 bidirectional Independent analog input/output channel 6 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
3 Z bidirectional Common analog output or input of the 8-channel switch; voltages at Z must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
4 Y7 bidirectional Independent analog input/output channel 7 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
5 Y5 bidirectional Independent analog input/output channel 5 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
6 E input Active-LOW enable input; a HIGH level switches all channels off, and the input clamp current for this pin is limited to ±10 mA when the input is below VSS - 0.5 V or above VDD + 0.5 V.
7 VEE power_in Supply voltage pin referenced to VDD, with a limiting value range of -18 V to +0.5 V.
8 VSS power_in Ground supply pin; all voltages in the datasheet are referenced to VSS = 0 V (ground).
9 S3 input Digital select input (binary channel select, S3 is the most significant bit of S3 S2 S1); the input voltage must stay between -0.5 V and VDD + 0.5 V, with input clamp current limited to ±10 mA.
10 S2 input Digital select input (binary channel select, S2 is the middle bit of S3 S2 S1); the input voltage must stay between -0.5 V and VDD + 0.5 V, with input clamp current limited to ±10 mA.
11 S1 input Digital select input (binary channel select, S1 is the least significant bit of S3 S2 S1); the input voltage must stay between -0.5 V and VDD + 0.5 V, with input clamp current limited to ±10 mA.
12 Y3 bidirectional Independent analog input/output channel 3 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
13 Y0 bidirectional Independent analog input/output channel 0 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
14 Y1 bidirectional Independent analog input/output channel 1 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
15 Y2 bidirectional Independent analog input/output channel 2 that connects to Z when selected by S1 to S3 with E LOW; Yn and Z voltages must not exceed VDD or VEE, and the input/output current is limited to ±10 mA.
16 VDD power_in Positive supply voltage, recommended 3 V to 15 V (absolute limiting range -0.5 V to +18 V referenced to VSS).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VDD 3 15 V see Fig. 7 6
input voltage VI 0 V 6
ambient temperature Tamb -40 125 °C in free air 6
input transition rise and fall rate Δt/ΔV 3.75 μs/V VDD = 5 V 6
input transition rise and fall rate Δt/ΔV 0.5 μs/V VDD = 10 V 6
input transition rise and fall rate Δt/ΔV 0.08 μs/V VDD = 15 V 6
supply voltage VDD -0.5 18 V 6
supply voltage VEE -18 0.5 V referenced to VDD 6
input clamping current IIK -10 10 mA pins Sn and E; VI < -0.5 V or VI > VDD + 0.5 V 6
input voltage VI -0.5 V 6
input/output current II/O -10 10 mA 6
supply current IDD 50 mA 6
storage temperature Tstg -65 150 °C 6
ambient temperature Tamb -40 125 °C 6
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 6
power dissipation per output P 100 mW 6
HIGH-level input voltage (VDD = 5 V) VIH 3.5 V /IO/ < 1 μA; Tamb = -40 °C 7
HIGH-level input voltage (VDD = 10 V) VIH 7 V /IO/ < 1 μA; Tamb = -40 °C 7
HIGH-level input voltage (VDD = 15 V) VIH 11 V /IO/ < 1 μA; Tamb = -40 °C 7
LOW-level input voltage (VDD = 5 V) VIL 1.5 V /IO/ < 1 μA; Tamb = -40 °C 7
LOW-level input voltage (VDD = 10 V) VIL 3 V /IO/ < 1 μA; Tamb = -40 °C 7
LOW-level input voltage (VDD = 15 V) VIL 4 V /IO/ < 1 μA; Tamb = -40 °C 7
input leakage current (VDD = 15 V) II -0.1 0.1 μA VDD = 15 V; Tamb = -40 °C 7
input leakage current (VDD = 15 V) II -1 1 μA VDD = 15 V; Tamb = 85 °C 7
OFF-state leakage current, Z port (VDD = 15 V), value in 25 °C max column IS(OFF) 1000 nA Z port; all channels OFF; see Fig. 8; VDD = 15 V 7
OFF-state leakage current, Y port (VDD = 15 V), value in 25 °C max column IS(OFF) 200 nA Y port; per channel; see Fig. 9; VDD = 15 V 7
supply current (VDD = 5 V) IDD 5 μA IO = 0 A; Tamb = -40 °C 7
supply current (VDD = 5 V) IDD 150 μA IO = 0 A; Tamb = 85 °C 7
supply current (VDD = 10 V) IDD 10 μA IO = 0 A; Tamb = -40 °C 7
supply current (VDD = 10 V) IDD 300 μA IO = 0 A; Tamb = 85 °C 7
supply current (VDD = 15 V) IDD 20 μA IO = 0 A; Tamb = -40 °C 7
supply current (VDD = 15 V) IDD 600 μA IO = 0 A; Tamb = 85 °C 7
input capacitance CI 7.5 pF Sn, E inputs 7
ON resistance (peak), VI = 0 V to VDD - VEE (VDD = 15 V) RON(peak) 60 175 Ω Tamb = 25 °C; ISW = 200 μA; VSS = VEE = 0 V; see Fig. 10 and Fig. 11 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin IIK input clamping current pins Sn and E; < -0.5 V or VI 6

CAD (KiCad official)

  • Symbol: HEF4051BTT
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: hef4051btt-etched.step / hef4051btt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4051btt.step / hef4051btt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 2ca4418589c3e483, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF