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HEF4050BT

Public Made by Adom

by adom

Nexperia Buffers, Drivers, Receivers, Transceivers, SOIC-16. Pinout settled in review by an AI reviewer against the manufacturer's datasheet, KiCad symbol/footprint/3D.

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Contents

README

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HEF4050BT

Nexperia · Buffers, Drivers, Receivers, Transceivers · SOIC-16

HEF4050BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage, recommended range 3 V to 15 V referenced to VSS (absolute maximum 0.5 V to +18 V).
2 1Y output Output of non-inverting buffer 1, with high current output capability suitable for driving TTL or high capacitive loads.
3 1A input Input of non-inverting buffer 1; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
4 2Y output Output of non-inverting buffer 2, with high current output capability suitable for driving TTL or high capacitive loads.
5 2A input Input of non-inverting buffer 2; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
6 3Y output Output of non-inverting buffer 3, with high current output capability suitable for driving TTL or high capacitive loads.
7 3A input Input of non-inverting buffer 3; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
8 VSS power_in Ground supply voltage, the reference for VDD (usually ground).
9 4A input Input of non-inverting buffer 4; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
10 4Y output Output of non-inverting buffer 4, with high current output capability suitable for driving TTL or high capacitive loads.
11 5A input Input of non-inverting buffer 5; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
12 5Y output Output of non-inverting buffer 5, with high current output capability suitable for driving TTL or high capacitive loads.
13 n.c. unconnected Not connected internally.
14 6A input Input of non-inverting buffer 6; input voltages may exceed VDD (absolute maximum input voltage 0.5 V to +18 V), and unused inputs must be connected to VDD, VSS, or another input.
15 6Y output Output of non-inverting buffer 6, with high current output capability suitable for driving TTL or high capacitive loads.
16 n.c. unconnected Not connected internally.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 4
Input clamping current IIK -10 mA VI < -0.5 V 4
Input voltage VI -0.5 18 V 4
Output clamping current IOK 10 mA VO < -0.5 V or VO > VDD + 0.5 V 4
Input/output current II/O 10 mA 4
Supply current IDD 50 mA 4
Storage temperature Tstg -65 150 °C 4
Ambient temperature Tamb -40 85 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +85 °C; SO16 package 4
Power dissipation per output P 100 mW 4
Supply voltage VDD 3 15 V 4
Input voltage VI 0 15 V 4
Ambient temperature Tamb -40 85 °C in free air 4
Input transition rise and fall rate t/V 3.75 µs/V VDD = 5 V 4
Input transition rise and fall rate t/V 0.5 µs/V VDD = 10 V 4
Input transition rise and fall rate t/V 0.08 µs/V VDD = 15 V 4
HIGH-level input voltage VIH 3.5 V IO < 1 µA; VDD = 5 V; Tamb = 25 °C 4
HIGH-level input voltage VIH 7 V IO < 1 µA; VDD = 10 V; Tamb = 25 °C 4
HIGH-level input voltage VIH 11 V IO < 1 µA; VDD = 15 V; Tamb = 25 °C 4
LOW-level input voltage VIL 1.5 V IO < 1 µA; VDD = 5 V; Tamb = 25 °C 4
LOW-level input voltage VIL 3 V IO < 1 µA; VDD = 10 V; Tamb = 25 °C 4
LOW-level input voltage VIL 4 V IO < 1 µA; VDD = 15 V; Tamb = 25 °C 4
HIGH-level output voltage VOH 4.95 V IO < 1 µA; VDD = 5 V; Tamb = 25 °C 5
HIGH-level output voltage VOH 9.95 V IO < 1 µA; VDD = 10 V; Tamb = 25 °C 5
HIGH-level output voltage VOH 14.95 V IO < 1 µA; VDD = 15 V; Tamb = 25 °C 5
LOW-level output voltage VOL 0.05 V IO < 1 µA; VDD = 5 V; Tamb = 25 °C 5
HIGH-level output current IOH 1.4 mA VO = 2.5 V; VDD = 5 V; Tamb = 25 °C 5
HIGH-level output current IOH 0.44 mA VO = 4.6 V; VDD = 5 V; Tamb = 25 °C 5
HIGH-level output current IOH 1.1 mA VO = 9.5 V; VDD = 10 V; Tamb = 25 °C 5
HIGH-level output current IOH 3 mA VO = 13.5 V; VDD = 15 V; Tamb = 25 °C 5
LOW-level output current IOL 2.9 mA VO = 0.4 V; VDD = 4.75 V; Tamb = 25 °C 5
LOW-level output current IOL 10 mA VO = 0.5 V; VDD = 10 V; Tamb = 25 °C 5
LOW-level output current IOL 20 mA VO = 1.5 V; VDD = 15 V; Tamb = 25 °C 5
Input leakage current II 0.3 µA VDD = 15 V; VI = VSS or VDD; Tamb = 25 °C 5
Supply current IDD 4 µA IO = 0 A; VDD = 5 V; Tamb = 25 °C 5
Supply current IDD 8 µA IO = 0 A; VDD = 10 V; Tamb = 25 °C 5
Supply current IDD 16 µA IO = 0 A; VDD = 15 V; Tamb = 25 °C 5
Input capacitance CI 7.5 pF 5
LOW-level output current IOL 2.3 mA VO = 0.4 V; VDD = 4.75 V; Tamb = 85 °C 5
LOW-level output current IOL 8 mA VO = 0.5 V; VDD = 10 V; Tamb = 85 °C 5
LOW-level output current IOL 16 mA VO = 1.5 V; VDD = 15 V; Tamb = 85 °C 5
Supply current IDD 30 µA IO = 0 A; VDD = 5 V; Tamb = 85 °C 5
Supply current IDD 60 µA IO = 0 A; VDD = 10 V; Tamb = 85 °C 5
Supply current IDD 120 µA IO = 0 A; VDD = 15 V; Tamb = 85 °C 5
HIGH to LOW propagation delay tPHL 35 70 ns nA to nY; see Figure 5; VDD = 5 V; Tamb = 25 °C; VSS = 0 V 5
HIGH to LOW propagation delay tPHL 20 35 ns nA to nY; see Figure 5; VDD = 10 V; Tamb = 25 °C; VSS = 0 V 5
HIGH to LOW propagation delay tPHL 15 30 ns nA to nY; see Figure 5; VDD = 15 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH propagation delay tPLH 55 110 ns nA to nY; see Figure 5; VDD = 5 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH propagation delay tPLH 25 55 ns nA to nY; see Figure 5; VDD = 10 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH propagation delay tPLH 20 40 ns nA to nY; see Figure 5; VDD = 15 V; Tamb = 25 °C; VSS = 0 V 5
HIGH to LOW output transition time tTHL 25 50 ns see Figure 5; VDD = 5 V; Tamb = 25 °C; VSS = 0 V 5
HIGH to LOW output transition time tTHL 10 20 ns see Figure 5; VDD = 10 V; Tamb = 25 °C; VSS = 0 V 5
HIGH to LOW output transition time tTHL 7 14 ns see Figure 5; VDD = 15 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH output transition time tTLH 60 120 ns see Figure 5; VDD = 5 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH output transition time tTLH 30 60 ns see Figure 5; VDD = 10 V; Tamb = 25 °C; VSS = 0 V 5
LOW to HIGH output transition time tTLH 20 40 ns see Figure 5; VDD = 15 V; Tamb = 25 °C; VSS = 0 V 5

CAD (KiCad official)

  • Symbol: HEF4050BT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hef4050bt-etched.step / hef4050bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4050bt.step / hef4050bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (12 pp, sha256 cee08a62f4003323, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF