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HEF4040BT

Public Made by Adom

by adom

Nexperia Counters / Dividers, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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HEF4040BT

Nexperia · Counters / Dividers · SOIC-16

HEF4040BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q11 output Parallel output bit 11 (highest stage, MSB of the 12-stage ripple counter). CMOS push-pull output; toggles every 4096 CP falling edges.
2 Q5 output Parallel output bit 5 of the ripple counter. CMOS push-pull output; toggles every 64 CP falling edges.
3 Q4 output Parallel output bit 4 of the ripple counter. CMOS push-pull output; toggles every 32 CP falling edges.
4 Q6 output Parallel output bit 6 of the ripple counter. CMOS push-pull output; toggles every 128 CP falling edges.
5 Q3 output Parallel output bit 3 of the ripple counter. CMOS push-pull output; toggles every 16 CP falling edges.
6 Q2 output Parallel output bit 2 of the ripple counter. CMOS push-pull output; toggles every 8 CP falling edges.
7 Q1 output Parallel output bit 1 of the ripple counter. CMOS push-pull output; toggles every 4 CP falling edges.
8 VSS power_in Ground supply voltage (0 V reference).
9 Q0 output Parallel output bit 0 (LSB of the 12-stage ripple counter). CMOS push-pull output; toggles on every HIGH-to-LOW transition of CP.
10 CP input Clock input (HIGH-to-LOW edge-triggered). The counter advances by one on each falling edge of CP.
11 MR input Master reset input, active HIGH. A HIGH on MR asynchronously clears all counter stages and forces all outputs Q0-Q11 LOW, independent of CP.
12 Q8 output Parallel output bit 8 of the ripple counter. CMOS push-pull output; toggles every 512 CP falling edges.
13 Q7 output Parallel output bit 7 of the ripple counter. CMOS push-pull output; toggles every 256 CP falling edges.
14 Q9 output Parallel output bit 9 of the ripple counter. CMOS push-pull output; toggles every 1024 CP falling edges.
15 Q10 output Parallel output bit 10 of the ripple counter. CMOS push-pull output; toggles every 2048 CP falling edges.
16 VDD power_in Positive supply voltage. Recommended operating range 3.0 V to 15.0 V; absolute maximum 18 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • HEF4040BTT

CAD (KiCad official)

  • Symbol: HEF4040BT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hef4040bt-etched.step / hef4040bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4040bt.step / hef4040bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 79a6d15b3b191c5c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF