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HEF4021BT

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Nexperia Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HEF4021BT

Nexperia · Registers · SOIC-16

HEF4021BT from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D7 input Parallel data input 7, asynchronously loaded into the register while PL is HIGH.
2 Q5 output Buffered parallel output from the sixth stage of the register.
3 Q7 output Buffered parallel output from the last (eighth) stage of the register.
4 D3 input Parallel data input 3, asynchronously loaded into the register while PL is HIGH.
5 D2 input Parallel data input 2, asynchronously loaded into the register while PL is HIGH.
6 D1 input Parallel data input 1, asynchronously loaded into the register while PL is HIGH.
7 D0 input Parallel data input 0, asynchronously loaded into the register while PL is HIGH.
8 VSS power_in Ground supply voltage (0 V reference).
9 PL input Asynchronous active HIGH parallel load input; loads D0 to D7 independent of CP and DS.
10 CP input Clock input, LOW-to-HIGH edge-triggered with Schmitt trigger action.
11 DS input Synchronous serial data input shifted into the first register position when PL is LOW.
12 Q6 output Buffered parallel output from the seventh stage of the register.
13 D4 input Parallel data input 4, asynchronously loaded into the register while PL is HIGH.
14 D5 input Parallel data input 5, asynchronously loaded into the register while PL is HIGH.
15 D6 input Parallel data input 6, asynchronously loaded into the register while PL is HIGH.
16 VDD power_in Supply voltage, recommended range 3 V to 15 V (absolute maximum 18 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 4
Input clamping current IIK -10 10 mA VI < -0.5 V or VI > VDD + 0.5 V 4
Output clamping current IOK -10 10 mA VO < -0.5 V or VO > VDD + 0.5 V 4
Input/output current II/O -10 10 mA 4
Supply current IDD 50 mA 4
Storage temperature Tstg -65 150 °C 4
Ambient temperature Tamb -40 125 °C 4
Total power dissipation Ptot 500 mW Tamb -40 °C to +125 °C; SO16 derates linearly with 12.4 mW/K above 110 °C 4
Power dissipation per output P 100 mW 4
Supply voltage VDD 3 15 V 5
Input voltage VI 0 V max = VDD 5
Ambient temperature Tamb -40 125 °C in free air 5
Input transition rise and fall rate Δt/ΔV 3.75 μs/V VDD = 5 V 5
Input transition rise and fall rate Δt/ΔV 0.5 μs/V VDD = 10 V 5
Input transition rise and fall rate Δt/ΔV 0.08 μs/V VDD = 15 V 5
HIGH-level input voltage VIH 3.5 V /IO/ < 1 μA; VDD = 5 V; Tamb = +25 °C 5
HIGH-level input voltage VIH 7 V /IO/ < 1 μA; VDD = 10 V; Tamb = +25 °C 5
HIGH-level input voltage VIH 11 V /IO/ < 1 μA; VDD = 15 V; Tamb = +25 °C 5
LOW-level input voltage VIL 1.5 V /IO/ < 1 μA; VDD = 5 V; Tamb = +25 °C 5
LOW-level input voltage VIL 3 V /IO/ < 1 μA; VDD = 10 V; Tamb = +25 °C 5
LOW-level input voltage VIL 4 V /IO/ < 1 μA; VDD = 15 V; Tamb = +25 °C 5
HIGH-level output voltage VOH 4.95 V /IO/ < 1 μA; VDD = 5 V; Tamb = +25 °C 5
HIGH-level output voltage VOH 9.95 V /IO/ < 1 μA; VDD = 10 V; Tamb = +25 °C 5
HIGH-level output voltage VOH 14.95 V /IO/ < 1 μA; VDD = 15 V; Tamb = +25 °C 5
LOW-level output voltage VOL 0.05 V /IO/ < 1 μA; VDD = 5 V, 10 V, 15 V; Tamb = +25 °C 5
HIGH-level output current IOH -1.4 mA VO = 2.5 V; VDD = 5 V; Tamb = +25 °C 5
HIGH-level output current IOH -0.5 mA VO = 4.6 V; VDD = 5 V; Tamb = +25 °C 5
HIGH-level output current IOH -1.3 mA VO = 9.5 V; VDD = 10 V; Tamb = +25 °C 5
HIGH-level output current IOH -3.4 mA VO = 13.5 V; VDD = 15 V; Tamb = +25 °C 5
LOW-level output current IOL 0.5 mA VO = 0.4 V; VDD = 5 V; Tamb = +25 °C 5
LOW-level output current IOL 1.3 mA VO = 0.5 V; VDD = 10 V; Tamb = +25 °C 5
LOW-level output current IOL 3.4 mA VO = 1.5 V; VDD = 15 V; Tamb = +25 °C 5
Input leakage current II -0.1 0.1 μA VDD = 15 V; Tamb = +25 °C 5
Input leakage current II -1 1 μA VDD = 15 V; Tamb = +125 °C 5
Supply current IDD 5 μA IO = 0 A; VDD = 5 V; Tamb = +25 °C 5
Supply current IDD 10 μA IO = 0 A; VDD = 10 V; Tamb = +25 °C 5
Supply current IDD 20 μA IO = 0 A; VDD = 15 V; Tamb = +25 °C 5
Supply current IDD 150 μA IO = 0 A; VDD = 5 V; Tamb = +125 °C 5
Supply current IDD 300 μA IO = 0 A; VDD = 10 V; Tamb = +125 °C 5
Supply current IDD 600 μA IO = 0 A; VDD = 15 V; Tamb = +125 °C 5
Input capacitance CI 7.5 pF Tamb = +25 °C 5
HIGH to LOW propagation delay tPHL 125 250 ns CP to Qn; VDD = 5 V 6
HIGH to LOW propagation delay tPHL 55 110 ns CP to Qn; VDD = 10 V 6
HIGH to LOW propagation delay tPHL 40 80 ns CP to Qn; VDD = 15 V 6
HIGH to LOW propagation delay tPHL 120 240 ns PL to Qn; VDD = 5 V 6
LOW to HIGH propagation delay tPLH 115 230 ns CP to Qn; VDD = 5 V 6
Transition time tt 60 120 ns Qn; VDD = 5 V 6
Set-up time tsu 50 25 ns Dn to PL; VDD = 5 V 6
Set-up time tsu 40 20 ns DS to CP; VDD = 5 V 6
Pulse width tW 70 35 ns CP = LOW; minimum width; VDD = 5 V 6
Recovery time trec 50 10 ns PL input; VDD = 5 V 6
Maximum clock frequency fclk(max) 6 13 MHz CP input; VDD = 5 V 7
Maximum clock frequency fclk(max) 15 30 MHz CP input; VDD = 10 V 7
Maximum clock frequency fclk(max) 20 40 MHz CP input; VDD = 15 V 7

CAD (KiCad official)

  • Symbol: HEF4021BT
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: hef4021bt-etched.step / hef4021bt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef4021bt.step / hef4021bt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 ca6449d387c0fc96, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF