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HEF40106BTT

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Nexperia Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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HEF40106BTT

Nexperia · Inverters · TSSOP-14

HEF40106BTT from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
2 1Y output Inverted output of buffer 1 (1Y = NOT 1A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
3 2A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
4 2Y output Inverted output of buffer 2 (2Y = NOT 2A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
5 3A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
6 3Y output Inverted output of buffer 3 (3Y = NOT 3A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
7 VSS power_in Ground reference, 0 V.
8 4Y output Inverted output of buffer 4 (4Y = NOT 4A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
9 4A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
10 5Y output Inverted output of buffer 5 (5Y = NOT 5A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
11 5A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
12 6Y output Inverted output of buffer 6 (6Y = NOT 6A); output clamping current is limited to ±10 mA and power dissipation per output to 100 mW.
13 6A input Schmitt-trigger inverter input with clamp diodes; input voltage must stay between VSS and VDD, and input clamping current is limited to ±10 mA.
14 VDD power_in Positive supply voltage; recommended 3 V to 15 V, absolute maximum -0.5 V to +18 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VDD -0.5 18 V 3
Input clamping current IIK -10 10 mA VI < -0.5 V or VI > VDD + 0.5 V 3
Input voltage VI -0.5 V 3
Output clamping current IOK -10 10 mA VO < -0.5 V or VO > VDD + 0.5 V 3
Input/output current II/O -10 10 mA 3
Supply current IDD 50 mA 3
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 3
Power dissipation per output P 100 mW 3
Supply voltage VDD 3 15 V 3
Input voltage VI 0 V 3
Ambient temperature in free air Tamb -40 125 °C 3
Positive-going threshold voltage at VDD 5 V VT+ 2 3 3.5 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Positive-going threshold voltage at VDD 10 V VT+ 3.7 5.8 7 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Positive-going threshold voltage at VDD 15 V VT+ 4.9 8.3 11 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Negative-going threshold voltage at VDD 5 V VT- 1.5 2.2 3 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Negative-going threshold voltage at VDD 10 V VT- 3 4.5 6.3 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Negative-going threshold voltage at VDD 15 V VT- 4 6.5 10.1 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Hysteresis voltage at VDD 5 V VH 0.5 0.8 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Hysteresis voltage at VDD 10 V VH 0.7 1.3 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
Hysteresis voltage at VDD 15 V VH 0.9 1.8 V VSS = 0 V; Tamb = -40 °C to +125 °C; see Fig. 5 and Fig. 6 7
HIGH to LOW propagation delay nA to nY at VDD 5 V tPHL 90 180 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 63 ns + (0.55 ns/pF)CL 5
HIGH to LOW propagation delay nA to nY at VDD 10 V tPHL 35 70 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 29 ns + (0.23 ns/pF)CL 5
HIGH to LOW propagation delay nA to nY at VDD 15 V tPHL 30 60 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 22 ns + (0.16 ns/pF)CL 5
LOW to HIGH propagation delay nA to nY at VDD 5 V tPLH 75 150 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 58 ns + (0.55 ns/pF)CL 5
LOW to HIGH propagation delay nA to nY at VDD 10 V tPLH 35 70 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 29 ns + (0.23 ns/pF)CL 5
LOW to HIGH propagation delay nA to nY at VDD 15 V tPLH 30 60 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 22 ns + (0.16 ns/pF)CL 5
HIGH to LOW output transition time nY to LOW at VDD 5 V tTHL 60 120 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 10 ns + (1.00 ns/pF)CL 5
HIGH to LOW output transition time nY to LOW at VDD 10 V tTHL 30 60 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 9 ns + (0.42 ns/pF)CL 5
HIGH to LOW output transition time nY to LOW at VDD 15 V tTHL 20 40 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 6 ns + (0.28 ns/pF)CL 5
LOW to HIGH output transition time nY to HIGH at VDD 5 V tTLH 60 120 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 10 ns + (1.00 ns/pF)CL 5
LOW to HIGH output transition time nY to HIGH at VDD 10 V tTLH 30 60 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 9 ns + (0.42 ns/pF)CL 5
LOW to HIGH output transition time nY to HIGH at VDD 15 V tTLH 20 40 ns Tamb = 25 °C; CL = 50 pF; tr = tf ≤ 20 ns; 6 ns + (0.28 ns/pF)CL 5
HIGH-level output voltage at VDD 5 V VOH 4.95 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
HIGH-level output voltage at VDD 10 V VOH 9.95 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
HIGH-level output voltage at VDD 15 V VOH 14.95 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
LOW-level output voltage at VDD 5 V VOL 0.05 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
LOW-level output voltage at VDD 10 V VOL 0.05 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
LOW-level output voltage at VDD 15 V VOL 0.05 V /IO/ < 1 μA; VSS = 0 V; VI = VSS or VDD 4
HIGH-level output current at VDD 5 V, Tamb -40 °C IOH -1.7 mA VO = 2.5 V; Tamb = -40 °C 4
HIGH-level output current at VDD 5 V, Tamb +125 °C IOH -1.1 mA VO = 2.5 V; Tamb = +125 °C 4
HIGH-level output current at VDD 5 V, Tamb -40 °C IOH -0.64 mA VO = 4.6 V; Tamb = -40 °C 4
HIGH-level output current at VDD 5 V, Tamb +125 °C IOH -0.36 mA VO = 4.6 V; Tamb = +125 °C 4
HIGH-level output current at VDD 10 V, Tamb -40 °C IOH -1.6 mA VO = 9.5 V; Tamb = -40 °C 4
HIGH-level output current at VDD 10 V, Tamb +125 °C IOH -0.9 mA VO = 9.5 V; Tamb = +125 °C 4
HIGH-level output current at VDD 15 V, Tamb -40 °C IOH -4.2 mA VO = 13.5 V; Tamb = -40 °C 4
HIGH-level output current at VDD 15 V, Tamb +125 °C IOH -2.4 mA VO = 13.5 V; Tamb = +125 °C 4
LOW-level output current at VDD 5 V, Tamb -40 °C IOL 0.64 mA VO = 0.4 V; Tamb = -40 °C 4
LOW-level output current at VDD 5 V, Tamb +125 °C IOL 0.36 mA VO = 0.4 V; Tamb = +125 °C 4
LOW-level output current at VDD 10 V, Tamb -40 °C IOL 1.6 mA VO = 0.5 V; Tamb = -40 °C 4
LOW-level output current at VDD 10 V, Tamb +125 °C IOL 0.9 mA VO = 0.5 V; Tamb = +125 °C 4
LOW-level output current at VDD 15 V, Tamb -40 °C IOL 4.2 mA VO = 1.5 V; Tamb = -40 °C 4
LOW-level output current at VDD 15 V, Tamb +125 °C IOL 2.4 mA VO = 1.5 V; Tamb = +125 °C 4
Input leakage current at VDD 15 V, Tamb -40 °C II -0.1 0.1 μA VDD = 15 V; VI = VSS or VDD; Tamb = -40 °C 4
Input leakage current at VDD 15 V, Tamb +125 °C II -1 1 μA VDD = 15 V; VI = VSS or VDD; Tamb = +125 °C 4
Supply current at VDD 5 V, Tamb -40 °C IDD 0.25 μA All valid input combinations; IO = 0 A; Tamb = -40 °C 4
Supply current at VDD 5 V, Tamb +125 °C IDD 7.5 μA All valid input combinations; IO = 0 A; Tamb = +125 °C 4
Supply current at VDD 10 V, Tamb -40 °C IDD 0.5 μA All valid input combinations; IO = 0 A; Tamb = -40 °C 4
Supply current at VDD 10 V, Tamb +125 °C IDD 15 μA All valid input combinations; IO = 0 A; Tamb = +125 °C 4
Supply current at VDD 15 V, Tamb -40 °C IDD 1 μA All valid input combinations; IO = 0 A; Tamb = -40 °C 4
Supply current at VDD 15 V, Tamb +125 °C IDD 30 μA All valid input combinations; IO = 0 A; Tamb = +125 °C 4

CAD (KiCad official)

  • Symbol: HEF40106BTT
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: hef40106btt-etched.step / hef40106btt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); hef40106btt.step / hef40106btt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (14 pp, sha256 385d3a3085506d62, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF